公开(公告)号：US09754868B2

公开(公告)日：2017-09-05

申请号：US15069387

申请日：2016-03-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Hsin-Chih Wang ,  Chih-Yuan Shih ,  Shih-Ching Chen

IPC: H01L21/50 ,  H01L23/498 ,  H01L21/48 ,  H01L21/304 ,  H01L21/306 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/304 ,  H01L21/306 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L2224/16225

Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.

公开(公告)号：US09748183B2

公开(公告)日：2017-08-29

申请号：US15455704

申请日：2017-03-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

公开(公告)号：US20170186703A1

公开(公告)日：2017-06-29

申请号：US15455704

申请日：2017-03-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

公开(公告)号：US20170040248A1

公开(公告)日：2017-02-09

申请号：US14817233

申请日：2015-08-04

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A met of fabricating an electronic package is provided, g: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing a portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since no temporary material is required. The present invention further provides the electronic package thus fabricated.

Abstract translation: 提供了一种制造电子封装的方法，其特征在于，提供一种载体，该载体体形成有形成有多个凹部的第一表面，以及与该第一表面相对的第二表面，并与该凹部相互连接。 在所述载体主体的第一表面上形成相应地具有容纳在所述凹部中的多个导电元件的电子结构; 以及从载体主体的第二表面露出的导电元件去除载体主体的一部分。 因此，由于不需要临时材料，因此保持了承载体，并且制造成本降低。 本发明还提供如此制造的电子封装。

公开(公告)号：US20160260644A1

公开(公告)日：2016-09-08

申请号：US14998324

申请日：2015-12-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Shan Chuang ,  Ching-Wen Chiang ,  Tzung-Yen Wu ,  Chun-Hung Lu

IPC: H01L23/053 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/06 ,  H01L23/498

CPC classification number: H01L23/053 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2224/83 ,  H01L2224/81

Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.

Abstract translation: 提供一种电子封装，包括电路部分，设置在电路部分上的电子元件和设置在电路部分上以覆盖电子元件的盖子部件。 在盖构件和电子元件之间形成分离部。 盖构件有助于防止整个包装结构的翘曲。 本发明还提供一种制造电子封装的方法。

公开(公告)号：US20160086903A1

公开(公告)日：2016-03-24

申请号：US14672268

申请日：2015-03-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/15153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a carrier, a semiconductor chip and an encapsulant. The semiconductor chip is disposed on the carrier, and has opposing non-active and active surfaces. The non-active surface is coupled to the carrier, and the active surface has a plurality of metallic pillars formed thereon. A under bump metallogy layer is formed between the metallic pillars and the active surface and on side surfaces of the metal pillars. The surface of the encapsulant is flush with end surfaces of the metallic pillars. Therefore, the product yield is increased significantly.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 半导体结构包括载体，半导体芯片和密封剂。 半导体芯片设置在载体上，并且具有相对的非活性和有效表面。 非活性表面耦合到载体，并且活性表面上形成有多个金属柱。 在金属柱和活性表面之间以及金属柱的侧表面上形成凸块下金属层。 密封剂的表面与金属柱的端面齐平。 因此，产品产量明显增加。

公开(公告)号：US20160049359A1

公开(公告)日：2016-02-18

申请号：US14744289

申请日：2015-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: An interposer is provided, including a substrate body, a plurality of conductive posts formed in the substrate body, and a plurality of conductive pads formed on the substrate body and electrically connected to the conductive posts. The conductive pads and the conductive posts are integrally formed. As such, no interface is formed between the conductive pads and the conductive posts, thereby preventing delamination or cracking from occurring between the conductive pads and the conductive posts.

Abstract translation: 提供了一种插入器，包括基板主体，形成在基板主体中的多个导电柱，以及形成在基板主体上并电连接到导电柱的多个导电焊盘。 导电焊盘和导电柱一体形成。 因此，在导电焊盘和导电柱之间没有形成界面，从而防止在导电焊盘和导电柱之间发生分层或破裂。