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49 条记录 (耗时 0.029 秒)

    Bus interface unit for reflecting state information for a transfer request to a requesting device
    23.
    发明授权
    Bus interface unit for reflecting state information for a transfer request to a requesting device 有权
    总线接口单元，用于将用于转发请求的状态信息反映到请求设备

    公开(公告)号：US06499077B1

    公开(公告)日：2002-12-24

    申请号：US09475964

    申请日：1999-12-30

    申请人： Darren L. Abramson ,  Mikal C. Hunsaker

    发明人： Darren L. Abramson ,  Mikal C. Hunsaker

    IPC分类号： G06F1300

    CPC分类号： G06F13/4059

    摘要： A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requester will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requester to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus. Once the transfer request is granted, it is sent over the host bus to its target while the associated state information is concurrently reflected back to the requestor to be used by the requester to complete the data or command information transfer.

    摘要翻译： 描述了用于操作设备及其组件的请求接口设备和方法。 请求接口设备包括总线接口单元（BIU）和请求设备。 请求设备生成数据或命令信息的传送请求，以及确定在授予传输请求之后请求者将传送数据或与请求相关联的命令信息的方式的状态信息。 转移请求和相关联的状态信息被发送到BIU，释放请求者产生新的请求，这是第一个转移请求等待被授予的请求。 传输请求和相关信息存储在BIU内的队列中，而BIU逻辑则可访问主机总线。 一旦传输请求被授权，它将通过主机总线发送到其目标，而相关联的状态信息被同时反射回请求者以供请求者用于完成数据或命令信息传送。

    Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field
    24.
    发明授权
    Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field 失效
    在总线复位后由计数器产生的自身ID代码与FIFO消息自身ID字段不同时，用于刷新FIFO中的DMA发送分组的方法/装置

    公开(公告)号：US06385671B1

    公开(公告)日：2002-05-07

    申请号：US09280781

    申请日：1999-03-29

    申请人： Mikal C. Hunsaker ,  Darren L. Abramson

    发明人： Mikal C. Hunsaker ,  Darren L. Abramson

    IPC分类号： G06F1300

    CPC分类号： H04L49/9094 ,  G06F13/28 ,  H04L49/90 ,  H04L49/901

    摘要： The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.

    摘要翻译： 本发明公开了一种用于处理从直接存储器访问（DMA）引擎接收的数据分组的方法和装置。 在一个实施例中，计数器产生自身ID码并且在总线复位之后增加自身ID码。 格式化器耦合到计数器以格式化包含自身ID字段的分组包（SOP）消息。 SOP消息对应于分组，并且自身ID字段对应于自身ID代码。 先进先出（FIFO）耦合到格式器以存储SOP消息和分组。 比较器耦合到FIFO以比较从FIFO读取的消息的自身ID字段与自身ID码。 耦合到FIFO的控制电路如果消息的自身ID字段不同于自身ID码，则刷新分组。

    Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails
    25.
    发明授权
    Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails 失效
    当写入错误队列已满时，物理写入数据包处理，发布写入数据包失败时发送写入错误队列存储物理写入请求

    公开(公告)号：US06366968B1

    公开(公告)日：2002-04-02

    申请号：US09105500

    申请日：1998-06-26

    申请人： Mikal C. Hunsaker

    发明人： Mikal C. Hunsaker

    IPC分类号： G06F1300

    CPC分类号： G06F11/0793 ,  G06F11/073 ,  G06F11/0745 ,  G06F2213/0012

    摘要： A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.

    摘要翻译： 描述用于处理写请求的系统。 系统使用两个队列来存储发布的写请求。 当发布发布的写入错误时，软件使用存储在两个队列的第一个队列中的信息来处理发布的写入错误。 产生发布的写入错误的写请求从继续处理包含写入请求的物理数据包的第二个队列中清除。

    Apparatuses for inter-component communication including slave component initiated transaction
    27.
    发明授权
    Apparatuses for inter-component communication including slave component initiated transaction 有权
    用于组件间通信的装置，包括从组件启动的交易

    公开(公告)号：US08892800B2

    公开(公告)日：2014-11-18

    申请号：US13436697

    申请日：2012-03-30

    申请人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

    发明人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

    IPC分类号： G06F13/00 ,  G06F13/364

    CPC分类号： G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

    摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed. A component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. Other embodiments may be disclosed or claimed.

    摘要翻译： 公开了具有组件间通信能力的分量设备和具有这种组件设备的系统。 组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 可以公开或要求保护其他实施例。

    AUTODETECTION OF A PCI EXPRESS DEVICE OPERATING AT A WIRELESS RF MITIGATION FREQUENCY
    29.
    发明申请
    AUTODETECTION OF A PCI EXPRESS DEVICE OPERATING AT A WIRELESS RF MITIGATION FREQUENCY 审中-公开
    在无线射频缓解频率下操作的PCI EXPRESS设备的自动检测

    公开(公告)号：US20110289241A1

    公开(公告)日：2011-11-24

    申请号：US13198528

    申请日：2011-08-04

    申请人： Mikal C. Hunsaker ,  Karthi Vadivelu ,  Andrew W. Martwick

    发明人： Mikal C. Hunsaker ,  Karthi Vadivelu ,  Andrew W. Martwick

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4295 ,  G06F2213/0026 ,  H04L7/10

    摘要： A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

    摘要翻译： 描述了检测符合PCI Express的端点设备的计算机系统。 具体地，计算机系统以第一频率对发射和接收电路进行计时，并启动训练序列。 如果端点设备以第一个频率成功列车，则端点设备符合PCI Express标准。 否则，计算机系统以第二频率发起另一训练序列。

    Rate control of flow control updates
    30.
    发明授权
    Rate control of flow control updates 有权
    流量控制更新的速率控制

    公开(公告)号：US07694049B2

    公开(公告)日：2010-04-06

    申请号：US11321362

    申请日：2005-12-28

    申请人： Chee How Goh ,  Thian Aun Tan ,  Mikal C. Hunsaker

    发明人： Chee How Goh ,  Thian Aun Tan ,  Mikal C. Hunsaker

    IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D50/20

    摘要： Various embodiments adjust the rate at which periodic flow control updates are transmitted when in a lower power or power saving state. One embodiment transmits flow control updates across a bus based upon a first rate in response to a normal power mode and transmits second flow control updates across the bus based upon a second rate in response to a power saving mode.

    摘要翻译： 各种实施例调节在处于较低功率或省电状态时周期性流量控制更新被传送的速率。 一个实施例基于响应于正常功率模式的第一速率跨总线传输流量控制更新，并且基于响应于省电模式的第二速率跨总线发送第二流控制更新。