公开(公告)号：US5703408A

公开(公告)日：1997-12-30

申请号：US419558

申请日：1995-04-10

申请人： Liu Ming-Tsung ,  Bill Y. B. Hsu ,  Hsien-Dar Chung ,  Der-Yuan Wu

发明人： Liu Ming-Tsung ,  Bill Y. B. Hsu ,  Hsien-Dar Chung ,  Der-Yuan Wu

IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49204

摘要： A structure and a process for forming an improved bonding pad which allows better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a window is formed defining a bonding pad area. The stripes promote an irregular surface in the barrier and metal layers which reduce stress between the dielectric layer, the barrier layer and the metal layer. Also, the irregular surfaces increase the barrier metal adhesion to the dielectric layer, reduce bond pad peel off, and increase bonding yields.

摘要翻译： 一种用于形成改进的接合焊盘的结构和工艺，其允许接合线和金属接合焊盘之间的更好的接合。 条纹形成在基板上。 在条纹上形成保形电介质层，保形阻挡层和金属层。 形成具有窗口的钝化层，限定了焊盘区域。 条纹促进阻挡层和金属层中的不规则表面，其减小介电层，阻挡层和金属层之间的应力。 此外，不规则表面增加了对电介质层的阻挡金属粘附性，减少了接合焊盘剥离，并增加了粘合产率。

公开(公告)号：US5599746A

公开(公告)日：1997-02-04

申请号：US239229

申请日：1994-05-06

申请人： Water Lur ,  Der-Yuan Wu

发明人： Water Lur ,  Der-Yuan Wu

IPC分类号： H01L21/301 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76889 ,  Y10S438/964

摘要： A method for eliminating the peeling of polycide at the edge of a wafer used to fabricate semi-conductors and integrated circuits. A global rough surface is formed on the wafer. The rough surface on the substrate wafer releases most of the thermal stress between the silicide and polysilicon layers which are found in conventional devices. A "peel free" surface results and the particle problem is lessened.

摘要翻译： 一种用于消除在用于制造半导体和集成电路的晶片的边缘处的多晶硅化合物的剥离的方法。 在晶片上形成全局粗糙表面。 衬底晶圆上的粗糙表面释放了常规器件中发现的硅化物和多晶硅层之间的大部分热应力。 “剥离”表面结果，粒子问题减弱。

公开(公告)号：US06746883B2

公开(公告)日：2004-06-08

申请号：US10064036

申请日：2002-06-04

申请人： Steve S. Chung ,  Shang-Jr Chen ,  Chien-Kuo Yang ,  Der-Yuan Wu

发明人： Steve S. Chung ,  Shang-Jr Chen ,  Chien-Kuo Yang ,  Der-Yuan Wu

IPC分类号： H01L2166

CPC分类号： G01R31/2621 ,  G01R31/2648 ,  G01R31/2831

摘要： A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for variousRTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.

摘要翻译： 已经实现了低泄漏电荷泵浦（CP）方法，用于在直接隧道状态下用超薄栅极氧化物直接确定超短栅极长度MOS器件中的界面陷阱。 可以从测量的CP电流中去除12Å-16Å栅极氧化物中的漏电流，从而可以准确测定界面陷阱。 已经成功地证明了这种方法成功地用于具有非常薄的栅极氧化物的各种RTNO生长和RPN处理的氧化物CMOS器件。 它可以用作超薄栅极氧化过程的良好监测器，以及与界面阱生成相关的器件可靠性的评估。 另外，目前的方法可以用来确定CMOS器件的物理通道长度。

公开(公告)号：US06406974B1

公开(公告)日：2002-06-18

申请号：US09535497

申请日：2000-03-24

申请人： Der-Yuan Wu ,  Jhy-Jeng Liu

发明人： Der-Yuan Wu ,  Jhy-Jeng Liu

IPC分类号： H01L21761

CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/0921

摘要： A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. Thus a triple N well is formed. A fourth ion implantation step is performed to form a cell well surrounded by the annular longitudinal deep N well. The cell well lies above the transversal deep N well. The second mask layer is removed.

摘要翻译： 描述了形成三重N阱的方法。 在基板上形成第一图案掩模层。 执行第一离子注入步骤以在衬底中形成环形纵向深N阱。 执行第二离子注入步骤以在衬底中形成环形纵向浅N阱。 环形纵向浅N井位于环形纵向深N井的上方。 第一个掩模层被去除。 在基板上形成第二图案化掩模层。 执行第三离子注入步骤以形成由环形纵向深N阱包围的横向深N阱。 横向深N井与环形纵深N井连接。 因此形成三重N阱。 执行第四离子注入步骤以形成由环形纵向深N阱围绕的阱。 细胞井位于横向深N井之上。 去除第二掩模层。

公开(公告)号：US06399495B1

公开(公告)日：2002-06-04

申请号：US09707249

申请日：2000-11-06

申请人： Ling-Hsu Tseng ,  Der-Yuan Wu

发明人： Ling-Hsu Tseng ,  Der-Yuan Wu

IPC分类号： H01L2144

CPC分类号： H01L21/76808 ,  H01L21/76807 ,  H01L21/76813 ,  H01L28/40

摘要： A method for forming a metal-insulator-metal (MIM) capacitor and an interconnect in integrated circuits is provided. First, a substrate with a plurality of conductive blocks under a surface of substrate is provided. Then, a first nitride layer is deposited on the substrate and then a first inter-metal-dielectric (IMD) layer is formed thereon. Next, a second nitride layer and a second IMD layer are sequentially formed on the first IMD layer. Thereafter, a first mask is formed on the second IMD layer with a first opening to expose the second IMD layer. Next, a first etching process is performed to form a via through the second IMD layer, the second nitride layer, the first IMD layer and the first nitride layer in the first opening to expose one of those conductive blocks. Then, a second etching process is performed to form a hole to expose the first nitride layer, wherein the hole is above one of those conductive blocks. Last, a conductive material is filled into the via and the hole to form the MIM capacitor and the interconnection.

摘要翻译： 提供了一种用于在集成电路中形成金属 - 绝缘体 - 金属（MIM）电容器和互连的方法。 首先，提供在基板表面下方具有多个导电块的基板。 然后，在衬底上沉积第一氮化物层，然后在其上形成第一金属间电介质（IMD）层。 接下来，在第一IMD层上依次形成第二氮化物层和第二IMD层。 此后，在第二IMD层上形成具有第一开口以露出第二IMD层的第一掩模。 接下来，执行第一蚀刻工艺以在第一开口中形成通过第二IMD层，第二氮化物层，第一IMD层和第一氮化物层的通孔，以暴露这些导电块之一。 然后，进行第二蚀刻工艺以形成一个露出第一氮化物层的孔，其中该孔在那些导电块中的一个之上。 最后，将导电材料填充到通孔和孔中以形成MIM电容器和互连。

公开(公告)号：US06261898B1

公开(公告)日：2001-07-17

申请号：US09654008

申请日：2000-09-01

申请人： Der-Yuan Wu

发明人： Der-Yuan Wu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/10873 ,  Y10S438/948 ,  Y10S438/949

摘要： A method of fabricating a salicide gate is provided, wherein a logic region and a memory cell region are formed on a substrate. A plurality of polysilicon gates and adjoining source/drain regions are also formed in both regions. A protection layer is formed to cover the polysilicon gates and the source/drain regions, followed by forming a photoresist layer on the substrate. A blanket defocus exposure is then conducted, whereby a part of the protection layer on the top surface of the polysilicon gates in both regions is eventually removed. Another photoresist layer is formed in the memory cell region, while the protection layer in the logic region is removed. A self-aligned silicide process is then conducted to form the salicide gates in both regions, and to selectively forming salicide layers on the source/drain regions in the logic region only.

摘要翻译： 提供一种制造硅化物栅极的方法，其中在衬底上形成逻辑区域和存储单元区域。 在两个区域中也形成多个多晶硅栅极和邻接的源极/漏极区域。 形成保护层以覆盖多晶硅栅极和源极/漏极区域，然后在衬底上形成光致抗蚀剂层。 然后进行全面的散焦曝光，由此最终去除两个区域中的多晶硅栅极顶表面上的保护层的一部分。 在存储单元区域中形成另一个光致抗蚀剂层，同时去除逻辑区域中的保护层。 然后进行自对准硅化物工艺以在两个区域中形成硅化物栅极，并且仅在逻辑区域中的源极/漏极区域上选择性地形成硅化物层。

公开(公告)号：US6124166A

公开(公告)日：2000-09-26

申请号：US340401

申请日：1999-06-28

申请人： Chuan-Fu Wang ,  Der-Yuan Wu

发明人： Chuan-Fu Wang ,  Der-Yuan Wu

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/84 ,  H01L28/91 ,  H01L27/10852

摘要： The present invention relates to a method of forming a lower electrode of a capacitor on a DRAM cell in a semiconductor wafer for increasing a surface area of the lower electrode. It is achieved by forming a second dielectric layer on a first polysilicon layer which comprises a plurality of doped horizontal layers along a vertical direction. Because dopant densities of the doped horizontal layers alternate in a high and low sequence, when forming a second polysilicon layer on the second dielectric layer, the second polysilicon layer will have many hemispherical grains on the vertical side wall of the second dielectric layer. This will result in an increased surface area of the lower electrode.

摘要翻译： 本发明涉及在用于增加下电极的表面积的半导体晶片中的DRAM单元上形成电容器的下电极的方法。 通过在第一多晶硅层上形成第二介质层来实现，该第一多晶硅层包括沿着垂直方向的多个掺杂的水平层。 由于掺杂水平层的掺杂浓度以高和低顺序交替，所以当在第二介电层上形成第二多晶硅层时，第二多晶硅层将在第二介电层的垂直侧壁上具有许多半球形晶粒。 这将导致下电极的表面积增加。

公开(公告)号：US6096642A

公开(公告)日：2000-08-01

申请号：US135496

申请日：1998-08-17

申请人： Der-Yuan Wu

发明人： Der-Yuan Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66545

摘要： A method is provided for forming self-aligned silicide in integrated circuit, which can help prevent the occurrence of a bridging effect in the integrated circuit. This method is characterized in the provision of an elevated spacer structure that can act like a barrier to prevent the occurrence of a bridging effect between the polysilicon gate and the source/drain regions caused by the forming of undesired silicide over the spacer structure due to lateral diffusion of the silicide from the polysilicon gate. Moreover, this method is characterized in the use of two different materials to respectively form the sacrificial layer and the field oxide layers, thus allowing the field oxide layers to remain substantially intact during the removal of the sacrificial layer through etching. This feature can help prevent the occurrence of leakage current from the metal plug to the substrate.

摘要翻译： 提供了一种用于在集成电路中形成自对准硅化物的方法，其可以有助于防止在集成电路中发生桥接效应。 该方法的特征在于提供一种可以像阻挡层一样起作用的高架隔离结构，以防止多晶硅栅极与源极/漏极区之间的桥接效应的产生，这是由于由于横向 硅化物从多晶硅栅极扩散。 此外，该方法的特征在于使用两种不同的材料来分别形成牺牲层和场氧化物层，从而允许场氧化物层在通过蚀刻去除牺牲层期间保持基本上完整。 该特征可以帮助防止从金属插塞到衬底的漏电流的发生。

公开(公告)号：US6080666A

公开(公告)日：2000-06-27

申请号：US274596

申请日：1999-03-23

申请人： Hal Lee ,  Der-Yuan Wu

发明人： Hal Lee ,  Der-Yuan Wu

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/76885

摘要： A method for increasing landing pad area is disclosed. Firstly, providing a fundamental structure, wherein shallow trench isolation (STI) is used and acting as an electrical isolation inside of substrate. Moreover, there are at least two gates with an isolation layer on top of the substrate and covered with a dielectric layer. Between the neighboring gates there is a contact hole that penetrates the dielectric layer from the top of the dielectric layer to the substrate. Taking this fundamental structure as the starting point for forming a conductor within the contact hole. Etching back the dielectric layer and exposing its top surface and a portion of sidewalls. Finally, a protection layer on top of the exposed portion of sidewalls of the conductor is formed in order to expand the landing pad area. After all, one would still be able to increase the landing pad area even though the distance between two gates is rather small. This method can solve all the puzzles caused by alignment accuray shift during post-process.

摘要翻译： 公开了一种增加着陆垫面积的方法。 首先，提供一种基本结构，其中使用浅沟槽隔离（STI）并且用作衬底内的电隔离。 此外，在衬底的顶部上至少有两个具有隔离层的栅极，并且被绝缘层覆盖。 在相邻的浇口之间有一个接触孔，该接触孔从电介质层的顶部到基底穿透电介质层。 将该基本结构作为在接触孔内形成导体的起点。 蚀刻介电层并暴露其顶表面和一部分侧壁。 最后，形成了在导体的侧壁的暴露部分的顶部上的保护层，以便扩大着陆焊盘区域。 毕竟，即使两个门之间的距离相当小，仍然可以增加着陆垫区域。 该方法可以解决后期处理中对准精度偏移引起的所有难题。

公开(公告)号：US5930623A

公开(公告)日：1999-07-27

申请号：US5449

申请日：1998-01-12

申请人： Der-Yuan Wu

发明人： Der-Yuan Wu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method is provided for use on a DRAM (dynamic random access memory) device for forming a data storage capacitor with a wide electrode area, and thus a high capacitance, for the DRAM device. The high capacitance allows the data storage capacitor to preserve high data retaining capability when the DRAM device is downsized for high integration. The method is characterized in the forming of silicon-nitride based sidewall spacers and polysilicon-based sidewall spacers in openings formed in oxide layers that allows the subsequently formed contact window to be narrowed to a reduced width, thereby preventing the subsequent etching process to damage the nearby polysilicon-based bit lines and gate electrodes due to misalignment in the etching. Moreover, the method allows the resultant data storage capacitor to have a wide electrode area that helps increase the capacitance thereof, thereby allowing the DRAM device to preserve a high and reliable data retaining capability to the data stored therein.

摘要翻译： 提供了一种用于DRAM（动态随机存取存储器）器件的方法，用于形成具有宽电极面积的数据存储电容器，因此用于DRAM器件的高电容。 当DRAM器件小型化以实现高集成度时，高电容允许数据存储电容器保持高数据保持能力。 该方法的特征在于在氧化物层中形成的开口中形成氮化硅基侧壁间隔物和基于多晶硅的侧壁间隔物，其允许随后形成的接触窗口变窄到减小的宽度，从而防止随后的蚀刻工艺损坏 附近的基于多晶硅的位线和栅电极由于蚀刻中的未对准。 此外，该方法允许所得到的数据存储电容器具有有助于增加其电容的宽电极面积，从而允许DRAM器件保存对其中存储的数据的高且可靠的数据保留能力。