公开(公告)号：US20230092132A1

公开(公告)日：2023-03-23

申请号：US17950027

申请日：2022-09-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hau Nguyen ,  Anindya Poddar

IPC: B81B3/00 ,  H01L23/00 ,  B81C3/00

Abstract: A described example includes: a MEMS component on a device side surface of a first semiconductor substrate; a second semiconductor substrate bonded to the device side surface of the first semiconductor substrate by a first seal patterned to form sidewalls that surround the MEMS component; a third semiconductor substrate having a second seal extending from a surface and bonded to the backside surface of the first semiconductor substrate by the second seal, the second seal forming sidewalls of a gap beneath the MEMS component. A trench extends through the first semiconductor substrate and at least partially surrounds the MEMS component. The third semiconductor substrate is mounted on a package substrate. A bond wire or ribbon bond couples the bond pad to a conductive lead on the package substrate; and mold compound covers the MEMS component, the bond wire, and a portion of the package substrate.

公开(公告)号：US11538717B2

公开(公告)日：2022-12-27

申请号：US17115730

申请日：2020-12-08

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Anindya Poddar ,  Usman Mahmood Chaudhry

IPC: H05K7/00 ,  H01L21/768 ,  H01L23/498 ,  H05K1/18 ,  B81B7/00 ,  H01L23/31 ,  H01L21/822 ,  H01L23/00 ,  H01L23/04

Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

公开(公告)号：US11158595B2

公开(公告)日：2021-10-26

申请号：US16028741

申请日：2018-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L23/538 ,  H01L23/433 ,  H01L23/367

Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

公开(公告)号：US20210134729A1

公开(公告)日：2021-05-06

申请号：US16669666

申请日：2019-10-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US10861741B2

公开(公告)日：2020-12-08

申请号：US15823149

申请日：2017-11-27

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Anindya Poddar ,  Usman Mahmood Chaudhry

IPC: H05K7/00 ,  H01L21/768 ,  H01L23/498 ,  H05K1/18 ,  B81B7/00 ,  H01L23/31 ,  H01L21/822 ,  H01L23/00 ,  H01L23/04

Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

公开(公告)号：US10763230B2

公开(公告)日：2020-09-01

申请号：US16228962

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US10734313B2

公开(公告)日：2020-08-04

申请号：US15951021

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Morroni ,  Rajeev Dinkar Joshi ,  Sreenivasan K. Koduri ,  Sujan Kundapur Manohar ,  Yogesh K. Ramadass ,  Anindya Poddar

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  H01L25/16 ,  H01L23/50

Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.

公开(公告)号：US20190237395A1

公开(公告)日：2019-08-01

申请号：US16378171

申请日：2019-04-08

Applicant: Texas Instruments Incorporated

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L25/16 ,  H01L21/48

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49544 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49589 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US10312184B2

公开(公告)日：2019-06-04

申请号：US14932055

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US20190164807A1

公开(公告)日：2019-05-30

申请号：US15823149

申请日：2017-11-27

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Anindya Poddar ,  Usman Mahmood Chaudhry

IPC: H01L21/768 ,  H01L23/498 ,  H05K1/18 ,  B81B7/00 ,  H01L23/04 ,  H01L23/31 ,  H01L21/822 ,  H01L23/00

Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.