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    Reset isolation for an embedded safety island in a system on a chip
    22.
    发明授权
    Reset isolation for an embedded safety island in a system on a chip 有权

    公开(公告)号：US11509302B2

    公开(公告)日：2022-11-22

    申请号：US17080239

    申请日：2020-10-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

    IPC: H03K17/22

    Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

    Apparatus and mechanism to bypass PCIe address translation by using alternative routing
    23.
    发明授权
    Apparatus and mechanism to bypass PCIe address translation by using alternative routing 有权

    公开(公告)号：US11449444B2

    公开(公告)日：2022-09-20

    申请号：US16559154

    申请日：2019-09-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

    IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

    System-on-chip (SoC) assembly, configurable IP generation and IP integration utilizing distributed computer systems
    24.
    发明授权
    System-on-chip (SoC) assembly, configurable IP generation and IP integration utilizing distributed computer systems 有权

    公开(公告)号：US11418409B2

    公开(公告)日：2022-08-16

    申请号：US17164925

    申请日：2021-02-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Todd Christopher Hiers ,  Chunhua Hu

    IPC: G06F3/00 ,  H04L41/22 ,  G06F3/0483 ,  G06F3/0486 ,  H04L41/12 ,  G06F30/30 ,  G06F3/01

    Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

    SYSTEM ON CHIP FIREWALL MEMORY ARCHITECTURE
    26.
    发明申请
    SYSTEM ON CHIP FIREWALL MEMORY ARCHITECTURE 有权

    公开(公告)号：US20210367922A1

    公开(公告)日：2021-11-25

    申请号：US17392497

    申请日：2021-08-03

    Applicant: Texas Instruments Incorporated

    Inventor： Amritpal Singh Mundra ,  Chunhua Hu

    IPC: H04L29/06

    Abstract: In described examples, a system on a chip (SoC) and method for sending messages in the SoC include determining locations of initiator-side firewall block and receiver-side firewall block memories using respective pointers to the firewall block memories stored in a single, contiguous memory. Addresses of the pointers within the single memory depend on respective unique firewall identifiers of the firewall blocks. An exclusive security configuration controller uses the pointers to configure the firewall blocks over a security bus which is electrically isolated from a system bus. The system bus is used to send messages from sending functional blocks to receiving functional blocks. The initiator-side firewall block adds a message identifier to messages. The message identifier depends on the initiator-side firewall block's configuration settings. The receiver-side firewall block controls permission for the receiving functional block to access the message, depending on the message identifier and the receiver-side firewall block's configuration settings.

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