中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

159 records (took 0.022 seconds)

    Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors
    22.
    发明授权
    Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors 有权
    通过分布式延迟检测和软错误校正保护存储器，数据通路和流水线寄存器以及其他存储元件

    公开(公告)号：US09557936B2

    公开(公告)日：2017-01-31

    申请号：US14587234

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran ,  Ramakrishnan Venkatasubramanian

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

    Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。

    Three-term predictive adder and/or subtracter
    23.
    发明授权
    Three-term predictive adder and/or subtracter 有权
    三项预测加法器和/或减法器

    公开(公告)号：US09448767B2

    公开(公告)日：2016-09-20

    申请号：US14192102

    申请日：2014-02-27

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

    IPC: G06F7/50 ,  G06F7/57 ,  G06F7/505 ,  G06F7/506

    CPC classification number: G06F7/57 ,  G06F7/5055 ,  G06F7/506

    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

    Abstract translation: 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

    Three-Term Predictive Adder and/or Subtracter
    24.
    发明申请
    Three-Term Predictive Adder and/or Subtracter 审中-公开
    三阶预测加法器和/或减法器

    公开(公告)号：US20140181165A1

    公开(公告)日：2014-06-26

    申请号：US14192102

    申请日：2014-02-27

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

    IPC: G06F7/57

    CPC classification number: G06F7/57 ,  G06F7/5055 ,  G06F7/506

    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

    Abstract translation: 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示波纹部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

    Deadlock-Avoiding Coherent System On Chip Interconnect
    26.
    发明申请
    Deadlock-Avoiding Coherent System On Chip Interconnect 有权
    死锁 - 避免相干系统片上互连

    公开(公告)号：US20140115272A1

    公开(公告)日：2014-04-24

    申请号：US14059732

    申请日：2013-10-22

    Applicant: Texas Instruments Incorporated

    Inventor： Matthew D. Pierson ,  Daniel B. Wu ,  Kai Chirca

    IPC: G06F12/08

    CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.

    Abstract translation: 本发明通过为窥探返回添加单独的非阻塞管道来缓解这些死锁问题。 这个单独的管道不会被阻塞在一致的请求之后。 本发明还重新分配主发起的流量以移动高速缓存驱逐（包括和不具有数据）和非相干写入到新的非阻塞信道。 这种非阻塞管道消除了在侦听请求到达内存控制器之前需要完成的任何一致的请求。 重新分区高速缓存启动的撤回到非阻塞管道可以同时发生侦听和撤离时防止死锁。 本发明的非阻塞信道组合来自存储器控制器发起的请求和主发起的驱逐/非相干写入的窥探响应。

    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    27.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 有权

    公开(公告)号：US20250103502A1

    公开(公告)日：2025-03-27

    申请号：US18976474

    申请日：2024-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Patent Agency Ranking