公开(公告)号：US20230283310A1

公开(公告)日：2023-09-07

申请号：US17828524

申请日：2022-05-31

Applicant: Texas Instruments Incorporated

Inventor： Siraj Akhtar

IPC: H04B1/12

CPC classification number: H04B1/123

Abstract: Power efficient receiver architectures are described. A receiver includes a first receiver path having a low power consumption compared to a second receiver path with a higher power consumption but a better ability to remove blocking signals. A multiplexer at the output of both receiver paths is used to select the digital bit stream from either the first path or the second path based on whichever path is currently enabled. The first receiver path can be enabled by default until a blocker signal is detected or the received data is invalid. At such an instance, the first receiver path is disabled and the second receiver path is enabled to remove the blocker and read out the data. The second receiver path may then continue to be enabled for a particular number of pings before switching the output back to the first receiver path.

公开(公告)号：US11671138B2

公开(公告)日：2023-06-06

申请号：US17489483

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： RR Manikandan ,  Kumar Anurag Shrivastava ,  Robert Floyd Payne ,  Anant Shankar Kamath ,  Swaminathan Sankaran ,  Kishalay Datta ,  Siraj Akhtar ,  Mark Edward Wentroble ,  Suvadip Banerjee ,  Rakesh Hariharan ,  Gurumurti Kailaschandra Avhad

IPC: H03K5/24 ,  H04B1/44 ,  H03K3/017 ,  H04L27/06 ,  H04L27/04

CPC classification number: H04B1/44 ,  H03K3/017 ,  H03K5/24 ,  H04L27/04 ,  H04L27/066

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

公开(公告)号：US11171636B2

公开(公告)日：2021-11-09

申请号：US16585155

申请日：2019-09-27

Applicant: Texas Instruments Incorporated

Inventor： Tolga Dinc ,  Salvatore Luciano Finocchiaro ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

IPC: H03K5/02 ,  H03K5/26 ,  G01R25/04 ,  H03H7/01 ,  H03K5/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

公开(公告)号：US20210203331A1

公开(公告)日：2021-07-01

申请号：US16731800

申请日：2019-12-31

Applicant: Texas Instruments Incorporated

Inventor： Salvatore Luciano Finocchiaro ,  Timothy Schmidl ,  Tolga Dinc ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

IPC: H03L7/099 ,  H03L7/08 ,  H03L7/093 ,  H04B1/40 ,  H04L7/033 ,  H04L27/12 ,  H04L27/14

Abstract: In described examples, a method of operating a transceiver with a transmitter and a receiver includes generating a frequency reference. In the transmitter: A phase locked loop (PLL) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference. A VCO in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PLL is locked to the transmitter VCO signal. In the receiver: A signal is received. A receiver VCO generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90° to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component.

公开(公告)号：US10979277B1

公开(公告)日：2021-04-13

申请号：US16731823

申请日：2019-12-31

Applicant: Texas Instruments Incorporated

Inventor： Timothy Mark Schmidl ,  Swaminathan Sankaran ,  Gerd Schuppener ,  Salvatore Luciano Finocchiaro ,  Siraj Akhtar ,  Tolga Dinc ,  Anand Ganesh Dabak ,  Baher Haroun

IPC: H04L27/38 ,  H04L25/03 ,  H04B7/005 ,  H03L7/191 ,  H03B5/32 ,  H03L7/087

Abstract: In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

公开(公告)号：US20200076374A1

公开(公告)日：2020-03-05

申请号：US16557571

申请日：2019-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siraj Akhtar ,  Swaminathan Sankaran

IPC: H03F1/26 ,  H03H11/28 ,  H03F3/183

Abstract: In an example apparatus, a first transistor has a base terminal, a first current terminal and a second current terminal. The base terminal is coupled to an input voltage node. A second transistor has a control terminal, a third current terminal and a fourth current terminal. The third current terminal is coupled to the second current terminal. The fourth current terminal is coupled to a first resistor. A second resistor is coupled to the control terminal. An inductor is coupled between the first resistor and a ground terminal.

公开(公告)号：US09900022B2

公开(公告)日：2018-02-20

申请号：US15408396

申请日：2017-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Diptendu Ghosh ,  Petteri Matti Litmanen ,  Siraj Akhtar

IPC: H03M1/66 ,  H03H7/01

CPC classification number: H03H7/0115 ,  H03M1/0631 ,  H03M1/66

Abstract: DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.

公开(公告)号：US20150280320A1

公开(公告)日：2015-10-01

申请号：US14734371

申请日：2015-06-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baher S. Haroun ,  Marco Corsi ,  Siraj Akhtar ,  Nirmal C. Warke

IPC: H01Q3/44 ,  H01Q9/04 ,  H01Q3/26

CPC classification number: H01Q3/44 ,  H01L23/3107 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/3011 ,  H01Q3/26 ,  H01Q9/0407 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Abstract translation: 在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。 然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。 该系统允许不对准，同时提供增加的通信带宽。

公开(公告)号：US20240105647A1

公开(公告)日：2024-03-28

申请号：US17954178

申请日：2022-09-27

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Siraj Akhtar ,  Rajen Murugan

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H03H7/01

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H03H7/0115 ,  H03H7/0138 ,  H01L24/16

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US20230124600A1

公开(公告)日：2023-04-20

申请号：US17702715

申请日：2022-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siraj Akhtar ,  Swaminathan Sankaran

IPC: H03H7/42 ,  H01F27/29 ,  H01P5/10 ,  H01L23/66 ,  H05K1/02

Abstract: In one example, an apparatus comprises: a first metal layer including a first segment and a second segment, in which the first segment is electrically coupled to a single-ended signal terminal, the second segment has a disconnected end; a second metal layer including a third segment and a fourth segment, in which the third segment is magnetically coupled to the first segment, the fourth segment is magnetically coupled to the second segment, a first end of the third segment and a first end of the fourth segment are electrically coupled at a center tap, and a second end of the third segment and a second end of the fourth segment are electrically coupled to respective first and second signal terminals of a pair of differential signal terminals; and a phase adjustment device proximate the center tap and electrically coupled to a second voltage reference terminal.