公开(公告)号：US12033936B2

公开(公告)日：2024-07-09

申请号：US17963149

申请日：2022-10-10

Applicant: Texas Instruments Incorporated

Inventor： Klaas De Haan ,  Mikhail Valeryevich Ivanov ,  Tobias Bernhard Fritz ,  Swaminathan Sankaran ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L21/50 ,  H01L23/50 ,  H04L25/02

CPC classification number: H01L23/5227 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5222 ,  H04L25/0268

Abstract: An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

公开(公告)号：US20240038691A1

公开(公告)日：2024-02-01

申请号：US17877426

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Gumaste Khanolkar ,  Anindya Poddar ,  Hassan Omar Ali ,  Dibyajat Mishra ,  Venkatesh Srinivasan ,  Swaminathan Sankaran

IPC: H01L23/66 ,  H01Q1/22 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01Q1/2283 ,  H01L21/565 ,  H01L21/561 ,  H01L24/96 ,  H01L24/97 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2223/6688 ,  H01L2924/2027 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.

公开(公告)号：US11863360B2

公开(公告)日：2024-01-02

申请号：US17584099

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Kumar Anurag Shrivastava ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Anant Shankar Kamath

IPC: H03C1/06 ,  H03C1/36 ,  H04L27/04

CPC classification number: H04L27/04 ,  H03C1/06 ,  H03C1/36

Abstract: An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.

公开(公告)号：US11799184B2

公开(公告)日：2023-10-24

申请号：US17140858

申请日：2021-01-04

Applicant: Texas Instruments Incorporated

Inventor： Baher Haroun ,  Juan Alejandro Herbsommer ,  Gerd Schuppener ,  Swaminathan Sankaran

IPC: H01P5/08 ,  H01P11/00 ,  H01P3/16

CPC classification number: H01P5/087 ,  H01P3/16 ,  H01P11/001

Abstract: An interposer acts as a buffer zone between a transceiver IC and a dielectric waveguide interconnect and establishes two well-defined reference planes that can be optimized independently. The interposer includes a block of material having: a first interface region to interface with an antenna coupled to an integrated circuit (IC); and a second interface region to interface to the dielectric waveguide. An interface waveguide is formed by a defined region positioned within the block of material between the first interface region and the second interface region.

公开(公告)号：US20230308323A1

公开(公告)日：2023-09-28

申请号：US17584099

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Kumar Anurag Shrivastava ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Anant Shankar Kamath

IPC: H04L27/04

CPC classification number: H04L27/04

Abstract: An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.

公开(公告)号：US11736144B2

公开(公告)日：2023-08-22

申请号：US17096886

申请日：2020-11-12

Applicant: Texas Instruments Incorporated

Inventor： Anand Dabak ,  Mahmoud Abdelmoneim Abdelmoneim Elgenedy ,  Timothy Mark Schmidl ,  Swaminathan Sankaran

IPC: H04B3/32 ,  H04L25/03

CPC classification number: H04B3/32 ,  H04L25/03057

Abstract: In described examples of a signal equalizer, a first filter stage is configured to perform adaptive equalization of crosstalk between a first signal component and a second signal component of a complex signal. A second filter stage is coupled serially to the first filter stage. The second equalizer stage is configured to perform separate adaptive equalization of the first signal component and separate adaptive equalization of the second signal component.

公开(公告)号：US11671138B2

公开(公告)日：2023-06-06

申请号：US17489483

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： RR Manikandan ,  Kumar Anurag Shrivastava ,  Robert Floyd Payne ,  Anant Shankar Kamath ,  Swaminathan Sankaran ,  Kishalay Datta ,  Siraj Akhtar ,  Mark Edward Wentroble ,  Suvadip Banerjee ,  Rakesh Hariharan ,  Gurumurti Kailaschandra Avhad

IPC: H03K5/24 ,  H04B1/44 ,  H03K3/017 ,  H04L27/06 ,  H04L27/04

CPC classification number: H04B1/44 ,  H03K3/017 ,  H03K5/24 ,  H04L27/04 ,  H04L27/066

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

公开(公告)号：US11456751B1

公开(公告)日：2022-09-27

申请号：US17536924

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Bichoy Bahr ,  Baher Haroun ,  Swaminathan Sankaran ,  Juan Alejandro Herbsommer

IPC: H03L7/099 ,  H03B5/32 ,  H03L7/08 ,  H03L7/14 ,  H03L7/10 ,  H03L7/06 ,  H03L1/00 ,  H03L1/02 ,  H03L7/00

Abstract: A reference frequency signal generator comprises a plurality of ovenized reference crystal oscillators (OCXOs) having different turn-over-temperatures, a selector logic circuit coupled to outputs of the OCXOs, a temperature sensor, and a controller coupled to an output of the temperature sensor. The selector logic circuit outputs one of the outputs of the OCXOs based on a control signal from the controller. The controller also generates control signals for the OCXOs. In some implementations, the reference frequency signal generator includes a phase-locked loop or a fractional output divider coupled to the output of the selector logic circuit and configured to receive a calibration signal from the controller.

公开(公告)号：US20220209750A1

公开(公告)日：2022-06-30

申请号：US17223792

申请日：2021-04-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Swaminathan Sankaran ,  Brad Kramer ,  Thomas Dyer Bonifield

IPC: H03H11/02 ,  H01L27/01 ,  H01L27/06

Abstract: An integrated circuit includes a substrate, a reference contact coupled to the substrate, a capacitor over the substrate, and a substrate element. The capacitor includes a first conductive element having an associated parasitic capacitance and a second conductive element electrically isolated from the first conductive element. The substrate element is coupled to the first conductive element by the parasitic capacitance and coupled to the reference contact. The substrate element includes a conductive doped region in the substrate and aligned with the first conductive element and the reference contact.

公开(公告)号：US11258154B2

公开(公告)日：2022-02-22

申请号：US16700476

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adam Joseph Fruehling ,  Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Swaminathan Sankaran

IPC: H01P5/107 ,  H01P3/12 ,  H01P5/02 ,  H01P7/06 ,  G04F5/14 ,  H01P1/20 ,  H01Q15/00

Abstract: An apparatus includes a substrate containing a cavity and a dielectric structure covering at least a portion of the cavity. The cavity is hermetically sealed. The apparatus also may include a launch structure formed on the dielectric structure and outside the hermetically sealed cavity. The launch structure is configured to cause radio frequency (RF) energy flowing in a first direction to enter the hermetically sealed cavity through the dielectric structure in a direction orthogonal to the first direction.