公开(公告)号：US20230395517A1

公开(公告)日：2023-12-07

申请号：US17805036

申请日：2022-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/5386 ,  H01L24/32 ,  H01L24/29 ,  H01L25/105 ,  H01L25/0652 ,  H01L24/83 ,  H01L21/76898 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/32146 ,  H01L2224/83896 ,  H01L2224/2919 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1432 ,  H01L2924/37001

Abstract: A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

公开(公告)号：US20230361015A1

公开(公告)日：2023-11-09

申请号：US18351809

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L24/09 ,  H01L21/486 ,  H01L2924/3511 ,  H01L2224/02379

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

公开(公告)号：US11804475B2

公开(公告)日：2023-10-31

申请号：US18175189

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/16 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80904 ,  H01L2224/9202 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US11728256B2

公开(公告)日：2023-08-15

申请号：US17808827

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/81815

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US11652037B2

公开(公告)日：2023-05-16

申请号：US17139775

申请日：2020-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Chen Lai ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L25/18 ,  H01L23/49816 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

公开(公告)号：US20230024043A1

公开(公告)日：2023-01-26

申请号：US17698611

申请日：2022-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/48

Abstract: Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

公开(公告)号：US20230023268A1

公开(公告)日：2023-01-26

申请号：US17654907

申请日：2022-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chipta Priya Laksana ,  Chun-Lung Jao ,  Shu-Shen Yeh ,  Chien-Sheng Chen ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L21/78 ,  H01L25/11

Abstract: A method includes forming an interconnect component including a plurality of dielectric layers that include an organic dielectric material, and a plurality of redistribution lines extending into the plurality of dielectric layers. The method further includes bonding a first package component and a second package component to the interconnect component, encapsulating the first package component and the second package component in an encapsulant, and precutting the interconnect component using a blade to form a trench. The trench penetrates through the interconnect component, and partially extends into the encapsulant. The method further includes performing a singulation process to separate the first package component and the second package component into a first package and a second package, respectively.

公开(公告)号：US11532593B2

公开(公告)日：2022-12-20

申请号：US17149348

申请日：2021-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Chien-Sheng Chen ,  Po-Yao Lin ,  Po-Chen Lai ,  Shu-Shen Yeh

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

公开(公告)号：US20220375843A1

公开(公告)日：2022-11-24

申请号：US17881981

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Hsien-Wen Liu ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Po-Yao Lin

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

公开(公告)号：US20220359489A1

公开(公告)日：2022-11-10

申请号：US17869968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.