公开(公告)号：US10714615B2

公开(公告)日：2020-07-14

申请号：US16222322

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US10461080B2

公开(公告)日：2019-10-29

申请号：US16053990

申请日：2018-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan Lee ,  Kuo-Yin Lin ,  Pin-Chuan Su ,  Teng-Chun Tsai

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, at first, a semiconductor substrate of a wafer is etched to form at least one fin. Then, an insulation structure is formed around the fin. Thereafter, the fin is recessed. Then, an epitaxial channel structure is epitaxially grown over the recessed fin. Thereafter, a portion of the epitaxial channel structure over a top surface of the insulation structure is removed. Then, a non-contact-type cleaning operation is performed to clean a top surface of the wafer after removing said portion of the epitaxial channel structure. Thereafter, the top surface of the wafer is cleaned using hydrogen fluoride after removing said portion of the epitaxial channel structure. Then, the insulation structure is recessed, such that the epitaxial channel structure protrudes from the recessed insulation structure.

公开(公告)号：US10164102B2

公开(公告)日：2018-12-25

申请号：US15959613

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L21/311 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US20180240909A1

公开(公告)日：2018-08-23

申请号：US15959613

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02631 ,  H01L21/30625 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US09768303B2

公开(公告)日：2017-09-19

申请号：US15226746

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84

CPC classification number: H01L29/7849 ,  H01L21/02631 ,  H01L21/30625 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US09748109B2

公开(公告)日：2017-08-29

申请号：US15047793

申请日：2016-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US09559021B2

公开(公告)日：2017-01-31

申请号：US15060807

申请日：2016-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/306 ,  B24B9/06 ,  B24B7/22 ,  B24B21/00

CPC classification number: H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

Abstract translation: 晶片抛光工艺包括抛光晶片背面的中心区域，抛光晶片背面的周边区域，抛光中心区域，以及抛光周边区域。 该过程可以显着减少划痕相关的晶片断裂，可以校正晶片上的焦点，并可以替代使用化学蚀刻剂的清洗工艺。 抛光和抛光可以包括抛光和抛光斜面区域。 进一步的改进包括用具有柔软背衬的研磨垫，抛光或抛光，具有相对较软的磨料颗粒的垫，抛光或抛光，其中由磨料颗粒制成的研磨垫已被分选并选择成规则形状，冲洗正被抛光的表面 用包含减摩剂的水溶液抛光，并用具有20k或更细砂粒或非研磨垫的研磨垫进行抛光。