公开(公告)号：US20100309704A1

公开(公告)日：2010-12-09

申请号：US12455762

申请日：2009-06-05

申请人： Sriram Dattaguru ,  Lesley A. Polka Wood ,  Yoshihiro Tomita ,  Kinya Ichikawa ,  Robert L. Sankman

发明人： Sriram Dattaguru ,  Lesley A. Polka Wood ,  Yoshihiro Tomita ,  Kinya Ichikawa ,  Robert L. Sankman

IPC分类号： G11C5/02 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/82 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01065 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

摘要翻译： 用于处理器的安装基板包括裸片侧和在裸片侧配置有处理器占位面的平台侧。 处理器占用面积耦合到至少一个处理器互连，并且微电子管芯嵌入在安装衬底中。 微电子管芯耦合到处理器互连，并且待处理器占用的处理器之间的通信速率在10Gb / s至1Tb / s之间。

公开(公告)号：US07345361B2

公开(公告)日：2008-03-18

申请号：US10728324

申请日：2003-12-04

申请人： Debendra Mallik ,  Kinya Ichikawa ,  Terry L. Sterrett ,  Johanna Swan

发明人： Debendra Mallik ,  Kinya Ichikawa ,  Terry L. Sterrett ,  Johanna Swan

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

摘要翻译： 系统可以包括集成电路管芯，耦合到集成电路管芯的集成电路封装，与集成电路管芯接触的模具化合物和集成电路封装以及耦合到集成电路封装的互连。 互连的第一部分可以与模具化合物接触，互连的第二部分可能不接触模具化合物，并且互连的第三部分可以与集成电路封装接触。

公开(公告)号：US20070231475A1

公开(公告)日：2007-10-04

申请号：US11395351

申请日：2006-03-31

申请人： Tadanori Shimoto ,  Kinya Ichikawa

发明人： Tadanori Shimoto ,  Kinya Ichikawa

IPC分类号： B41M5/00 ,  B05D1/32 ,  B05D1/36

CPC分类号： H01L23/4828 ,  H01L21/4867 ,  H01L23/49811 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/095 ,  H05K1/162 ,  H05K3/246 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09763 ,  H01L2924/00

摘要： In some embodiments, conductor structure on dielectric material is presented. In this regard, a substrate in introduced having a conductive paste layer to adhere to dielectric material without a micro-anchor. Other embodiments are also disclosed and claimed.

摘要翻译： 在一些实施例中，介绍了电介质材料上的导体结构。 在这方面，引入的基板具有导电浆料层以粘附到没有微锚的电介质材料上。 还公开并要求保护其他实施例。

公开(公告)号：US20060191134A1

公开(公告)日：2006-08-31

申请号：US11413848

申请日：2006-04-28

申请人： Kinya Ichikawa

发明人： Kinya Ichikawa

IPC分类号： H01R12/00 ,  H01K3/10 ,  H05K3/30

CPC分类号： H05K3/3436 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01R12/714 ,  H05K1/141 ,  H05K3/305 ,  H05K2201/0394 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

摘要： Embodiments include a generally planar patch substrate having external connection pads on one side, electrical connections connected to the external connection pads and extending through the substrate, and plated contacts formed on the electrical connections and extending beyond the other side of the patch substrate. The external connection pads may be connected to one electrical device using solder bumps or balls, and the plated contacts may be connected to contacts of another electrical device by thermo-compression bonding. Also, a surface of the patch substrate having the plated contacts may be attached to the other electrical device using an electrically insulating adhesive. Moreover, the plated contacts may have a smaller surface area than the external connection pads, so that the other electrical device can also have smaller contacts, leaving more space for electrically conductive traces to the contacts on the surface and within layers of the other electrical device.

摘要翻译： 实施例包括在一侧具有外部连接焊盘的大致平面的贴片衬底，连接到外部连接焊盘并延伸穿过衬底的电连接以及形成在电连接上并延伸超过贴片衬底的另一侧的电镀触点。 外部连接焊盘可以使用焊料凸块或球连接到一个电气设备，并且电镀触点可以通过热压接而连接到另一个电气设备的触点。 此外，具有电镀触点的贴片基板的表面可以使用电绝缘粘合剂附接到另一电气装置。 此外，电镀触点可以具有比外部连接焊盘更小的表面积，使得另一个电气装置也可以具有更小的触点，为导电迹线留下更多的空间用于表面上的触点和另一个电气装置的层内 。

公开(公告)号：US06342791B1

公开(公告)日：2002-01-29

申请号：US09501243

申请日：2000-02-10

申请人： Kinya Ichikawa ,  Koichiro Kurata ,  Suteo Fujino ,  Chihiro Okado ,  Takatomo Izume ,  Yasuo Sakata

发明人： Kinya Ichikawa ,  Koichiro Kurata ,  Suteo Fujino ,  Chihiro Okado ,  Takatomo Izume ,  Yasuo Sakata

IPC分类号： G01R3126

CPC分类号： G01R31/2632 ,  G01R31/27

摘要： This invention is a diode defect detecting device including a current detector for detecting the primary current of a transformer, a comparator for comparing the detection current detected by the current detector with a current reference and outputting a reset signal if the detection current is larger than the current reference, an oscillator for generating a clock signal, a flip-flop circuit for receiving a set signal on the basis of a front and an end edge of the clock signal generated by the oscillator and receiving the output reset signal from the comparator, a polarity changing circuit for outputting a polarity changing signal for changing the polarities of the plurality of diodes on the basis of the output clock signal from the flip-flop circuit, and a determination circuit for calculating, in order to detect malfunctions of the plurality of diodes, any impedance change on the secondary side viewed from the primary side of the transformer on the basis of the pulse width of each polarity of the output clock signal from the flip-flop circuit.

摘要翻译： 本发明是一种二极管缺陷检测装置，其包括用于检测变压器的初级电流的电流检测器，用于将由电流检测器检测的检测电流与电流基准进行比较的比较器，并且如果检测电流大于 电流基准，用于产生时钟信号的振荡器，用于基于由振荡器产生的时钟信号的前沿和结束沿接收设置信号的触发器电路，并从比较器接收输出复位信号; 极性改变电路，用于根据来自触发器电路的输出时钟信号输出用于改变多个二极管的极性的极性改变信号;以及确定电路，用于计算，以便检测多个二极管的故障 基于每个p的脉冲宽度从变压器的初级侧观察的次级侧的任何阻抗变化 来自触发器电路的输出时钟信号的极性。