公开(公告)号：US06342791B1

公开(公告)日：2002-01-29

申请号：US09501243

申请日：2000-02-10

申请人： Kinya Ichikawa ,  Koichiro Kurata ,  Suteo Fujino ,  Chihiro Okado ,  Takatomo Izume ,  Yasuo Sakata

发明人： Kinya Ichikawa ,  Koichiro Kurata ,  Suteo Fujino ,  Chihiro Okado ,  Takatomo Izume ,  Yasuo Sakata

IPC分类号： G01R3126

CPC分类号： G01R31/2632 ,  G01R31/27

摘要： This invention is a diode defect detecting device including a current detector for detecting the primary current of a transformer, a comparator for comparing the detection current detected by the current detector with a current reference and outputting a reset signal if the detection current is larger than the current reference, an oscillator for generating a clock signal, a flip-flop circuit for receiving a set signal on the basis of a front and an end edge of the clock signal generated by the oscillator and receiving the output reset signal from the comparator, a polarity changing circuit for outputting a polarity changing signal for changing the polarities of the plurality of diodes on the basis of the output clock signal from the flip-flop circuit, and a determination circuit for calculating, in order to detect malfunctions of the plurality of diodes, any impedance change on the secondary side viewed from the primary side of the transformer on the basis of the pulse width of each polarity of the output clock signal from the flip-flop circuit.

摘要翻译： 本发明是一种二极管缺陷检测装置，其包括用于检测变压器的初级电流的电流检测器，用于将由电流检测器检测的检测电流与电流基准进行比较的比较器，并且如果检测电流大于 电流基准，用于产生时钟信号的振荡器，用于基于由振荡器产生的时钟信号的前沿和结束沿接收设置信号的触发器电路，并从比较器接收输出复位信号; 极性改变电路，用于根据来自触发器电路的输出时钟信号输出用于改变多个二极管的极性的极性改变信号;以及确定电路，用于计算，以便检测多个二极管的故障 基于每个p的脉冲宽度从变压器的初级侧观察的次级侧的任何阻抗变化 来自触发器电路的输出时钟信号的极性。

公开(公告)号：US20070001277A1

公开(公告)日：2007-01-04

申请号：US11173657

申请日：2005-06-30

申请人： Kinya Ichikawa

发明人： Kinya Ichikawa

IPC分类号： H01L23/495

CPC分类号： H01L23/49833 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/0733 ,  Y02P70/613

摘要： In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，组装堆叠的堆叠包括第一集成电路封装以及将集成电路封装连接到电路板的衬底连接器。 在一个实施例中，衬底连接器包括插入器衬底和接合到插入器衬底的贴片衬底。 每个衬底包括延伸穿过衬底以连接到另一层的柱形导体。 描述和要求保护其他实施例。

公开(公告)号：US07132311B2

公开(公告)日：2006-11-07

申请号：US10206007

申请日：2002-07-26

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L21/56

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US20050121764A1

公开(公告)日：2005-06-09

申请号：US10728324

申请日：2003-12-04

申请人： Debendra Mallik ,  Kinya Ichikawa ,  Terry Sterrett ,  Johanna Swan

发明人： Debendra Mallik ,  Kinya Ichikawa ,  Terry Sterrett ,  Johanna Swan

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

摘要翻译： 系统可以包括集成电路管芯，耦合到集成电路管芯的集成电路封装，与集成电路管芯接触的模具化合物和集成电路封装以及耦合到集成电路封装的互连。 互连的第一部分可以与模具化合物接触，互连的第二部分可能不接触模具化合物，并且互连的第三部分可以与集成电路封装接触。

公开(公告)号：US20050287829A1

公开(公告)日：2005-12-29

申请号：US10881243

申请日：2004-06-29

申请人： Kinya Ichikawa

发明人： Kinya Ichikawa

IPC分类号： H01R12/00 ,  H05K1/14 ,  H05K3/30 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01R12/714 ,  H05K1/141 ,  H05K3/305 ,  H05K2201/0394 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

摘要： Embodiments include a generally planar patch substrate having external connection pads on one side, electrical connections connected to the external connection pads and extending through the substrate, and plated contacts formed on the electrical connections and extending beyond the other side of the patch substrate. The external connection pads may be connected to one electrical device using solder bumps or balls, and the plated contacts may be connected to contacts of another electrical device by thermo-compression bonding. Also, a surface of the patch substrate having the plated contacts may be attached to the other electrical device using an electrically insulating adhesive. Moreover, the plated contacts may have a smaller surface area than the external connection pads, so that the other electrical device can also have smaller contacts, leaving more space for electrically conductive traces to the contacts on the surface and within layers of the other electrical device.

摘要翻译： 实施例包括在一侧具有外部连接焊盘的大致平面的贴片衬底，连接到外部连接焊盘并延伸穿过衬底的电连接以及形成在电连接上并延伸超过贴片衬底的另一侧的电镀触点。 外部连接焊盘可以使用焊料凸块或球连接到一个电气设备，并且电镀触点可以通过热压接而连接到另一个电气设备的触点。 此外，具有电镀触点的贴片基板的表面可以使用电绝缘粘合剂附接到另一电气装置。 此外，电镀触点可以具有比外部连接焊盘更小的表面积，使得另一个电气装置也可以具有更小的触点，为导电迹线留下更多的空间用于表面上的触点和另一个电气装置的层内 。

公开(公告)号：US20050217787A1

公开(公告)日：2005-10-06

申请号：US11143379

申请日：2005-06-01

申请人： Yukihiro Murakami ,  Kinya Ichikawa

发明人： Yukihiro Murakami ,  Kinya Ichikawa

IPC分类号： H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L21/44 ,  B32B31/00

CPC分类号： H01L25/0657 ,  H01L23/4985 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： In one embodiment of the invention, a die is bonded on a strip carrier frame having a carrier alignment landmark. A tape automated bonding (TAB) strip having a TAB alignment landmark is aligned with the strip carrier frame. The TAB strip is bonded to the strip carrier frame to form a bonded unit.

摘要翻译： 在本发明的一个实施例中，管芯结合在具有载体对准界标的带状载体框架上。 具有TAB对准界标的胶带自动粘合（TAB）条带与带状载体框架对准。 TAB条被粘合到带状载体框架上以形成粘合单元。

公开(公告)号：US06785148B1

公开(公告)日：2004-08-31

申请号：US09217401

申请日：1998-12-21

申请人： Kenzo Ishida ,  Shuji Inoue ,  Kinya Ichikawa ,  Kenji Takahashi

发明人： Kenzo Ishida ,  Shuji Inoue ,  Kinya Ichikawa ,  Kenji Takahashi

IPC分类号： H05K710

CPC分类号： H05K3/325 ,  H01R12/52 ,  H01R13/2414 ,  H05K3/305 ,  H05K3/4069 ,  H05K7/1061 ,  H05K2201/0314 ,  H05K2201/10265 ,  H05K2201/10378

摘要： A socket for mounting a processor and/or a board has a substrate with a built in socket. The socket has conductive, elastically deformable terminals. The socket may be mounted to a processor and a board without using conventional surface mount technology, instead providing a mechanical contact mechanism between the socket and the board or processor. An adhesive layer may also be used to connect the socket to a processor and/or a board.

摘要翻译： 用于安装处理器和/或板的插座具有带有内置插座的基板。 插座具有导电的，可弹性变形的端子。 插座可以安装到处理器和板上，而不使用传统的表面贴装技术，而是在插座和板或处理器之间提供机械接触机构。 也可以使用粘合剂层将插座连接到处理器和/或板。

公开(公告)号：US06632704B2

公开(公告)日：2003-10-14

申请号：US09741535

申请日：2000-12-19

申请人： Takashi Kumamoto ,  Kinya Ichikawa

发明人： Takashi Kumamoto ,  Kinya Ichikawa

IPC分类号： H01L2144

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L21/563 ,  H01L21/565 ,  H01L24/28 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, preferably epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

摘要翻译： 描述了用于制造模制倒装芯片封装的方法。 将包括薄基板和硅芯片的不完全倒装芯片封装放置在模具中。 将树脂（优选环氧树脂）注入填充倒装芯片的表面与相邻基底之间的间隙的模具中。 此外，形成加强结构以提高薄衬底的整体刚度和整体的包装。

公开(公告)号：US20150270169A1

公开(公告)日：2015-09-24

申请号：US14219749

申请日：2014-03-19

申请人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Robert L. Sankman ,  Eric Li

发明人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Robert L. Sankman ,  Eric Li

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/381

摘要： A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.

摘要翻译： 一种制造电子封装的方法。 该方法包括用电导体填充模具以在模具内形成多个电互连。 模具包括填充有多个电导体以形成多个电互连的开口。 制造电子封装的方法还包括将模具附接到基板，使得电互连件接合基板上的电触点。 制造电子封装的方法还可以包括在电绝缘体上形成接合电互连并将管芯连接到衬底上的导电焊盘，使得管芯电连接到至少一些电互连。

公开(公告)号：US07495330B2

公开(公告)日：2009-02-24

申请号：US11173657

申请日：2005-06-30

申请人： Kinya Ichikawa

发明人： Kinya Ichikawa

IPC分类号： H01L23/04

CPC分类号： H01L23/49833 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/0733 ,  Y02P70/613

摘要： In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，组装堆叠的堆叠包括第一集成电路封装以及将集成电路封装连接到电路板的衬底连接器。 在一个实施例中，衬底连接器包括插入器衬底和接合到插入器衬底的贴片衬底。 每个衬底包括延伸穿过衬底以连接到另一层的柱形导体。 描述和要求保护其他实施例。