公开(公告)号：US4739250A

公开(公告)日：1988-04-19

申请号：US932261

申请日：1986-11-19

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H03K19/177 ,  G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318516

Abstract: A semiconductor integrated circuit device with a test circuit including: a plurality of basic gate cells arranged in a matrix; wiring connected between the basic gate cells and arranged so as to constitute a logic circuit; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells. The test circuit comprises: a test input section having a plurality of row selection wires provided along the basic gate cells in a row direction, a plurality of column selection wires provided along the basic gate cells in a column direction, and an access circuit connected to an input portion of the basic gate cell for applying an input signal to the basic gate cell optionally selected by the row and column selection wires; and a test direction section having a plurality of monitor wires provided along the basic gate cells in the row direction and a switching element connected between the basic gate cell and the monitor wire.

Abstract translation: 一种具有测试电路的半导体集成电路器件，包括：以矩阵排列的多个基本栅极单元; 连接在基本门单元之间并布置成构成逻辑电路的布线; 以及用于检查每个门单元的操作状态和基本门单元之间的连接状态的测试电路。 测试电路包括：测试输入部分，具有沿着行方向的基本栅极单元设置的多个行选择线，沿着列方向沿着基本门单元设置的多个列选择线，以及连接到 基本门单元的输入部分，用于将输入信号施加到由行和列选择线可选地选择的基本门单元; 以及测试方向部分，具有沿着行方向的基本栅极单元设置的多条监视线，以及连接在基本门单元和监视器线之间的开关元件。

公开(公告)号：US4682202A

公开(公告)日：1987-07-21

申请号：US635680

申请日：1984-07-30

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10 ,  H01L29/70 ,  H01L29/78

CPC classification number: H01L21/82 ,  H01L27/11896

Abstract: A master slice IC device comprising at least two kind of basic cells; that is, a first kind of basic cells each having one or more n-type MIS transistors and one or more p-type MIS transistors to form a CMIS logic circuit, and a second kind of basic cells each comprising an npn-type bipolar transistor and a pnp-type bipolar transistor to form a bipolar buffer circuit having a large drive ability. The second kind of basic cells are used, for example, only when the fan-out number is large and/or the length of the connection lines is long, thereby realizing a high degree of freedom in circuit design and a high operating speed without increasing the power consumption.

Abstract translation: 一种主切片IC器件，包括至少两种基本单元; 也就是说，具有一个或多个n型MIS晶体管和一个或多个p型MIS晶体管以形成CMIS逻辑电路的第一种基本单元，以及每个包括npn型双极晶体管的第二种基本单元 和pnp型双极晶体管，以形成具有大驱动能力的双极型缓冲电路。 使用第二种基本单元，例如，仅当扇出数量大和/或连接线的长度较长时，才能实现电路设计的高自由度和高的运行速度，而不会增加 功耗。

公开(公告)号：US4535258A

公开(公告)日：1985-08-13

申请号：US408846

申请日：1982-08-17

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H03K19/013 ,  H03K19/088 ,  H03K17/04 ,  H03K19/092

CPC classification number: H03K19/088 ,  H03K19/0136

Abstract: A transistor circuit including a pull-down circuit. The pull-down circuit functions to discharge electric charges stored in a base of an output transistor of the transistor circuit and comprises a control transistor, a two-terminal unit (impedance means), and a resistor. The stored electric charges are discharged to ground by way of the two-terminal unit and the resistor. The stored electric charges can be discharged selectively when the output transistor is turned off, with the aid of the control transistor.

Abstract translation: 一种包括下拉电路的晶体管电路。 下拉电路用于放电存储在晶体管电路的输出晶体管的基极中的电荷，并且包括控制晶体管，二端单元（阻抗装置）和电阻器。 存储的电荷通过两端单元和电阻器放电到地。 借助于控制晶体管，当输出晶体管截止时，存储的电荷可以被选择性放电。

公开(公告)号：US5917729A

公开(公告)日：1999-06-29

申请号：US964318

申请日：1997-11-04

Applicant: Masayuki Naganuma ,  Tetsu Tanizawa

Inventor： Masayuki Naganuma ,  Tetsu Tanizawa

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118

CPC classification number: G06F17/5068

Abstract: A method of placing and routing elements of a semiconductor integrated circuit picks out a signal net, a driver of the signal net, and load cells driven by the driver among the elements of the integrated circuit, places the driver at a first position, defines a first range based on the first position, determines a second position in the first range, defines a second range based on the second position, and collectively places the load cells of a predetermined number in the second range. Namely, the method deals with a signal net in the integrated circuit, a driver of the net, and load cells driven by the driver. The method sets conditions on the signal net, driver, and load cells, when placing and routing the elements of the integrated circuit, to thereby reduce skew (skew time), wiring overhead, and time delay in the integrated circuit and speedily and easily place and route the elements.

Abstract translation: 放置和布线半导体集成电路的元件的方法从集成电路的元件中选出信号网，信号网的驱动器和由驱动器驱动的负载单元，将驱动器置于第一位置，定义一个 基于第一位置的第一范围确定第一范围中的第二位置，基于第二位置限定第二范围，并且将预定数量的称重传感器集中地放置在第二范围内。 即，该方法处理集成电路中的信号网，网络的驱动器和由驱动器驱动的负载传感器。 该方法在放置和布线集成电路的元件时，对信号网，驱动器和称重传感器设置条件，从而减少集成电路中的偏斜（歪斜时间），接线开销和时间延迟，并快速方便地放置 并路由元素。

公开(公告)号：US5852445A

公开(公告)日：1998-12-22

申请号：US552150

申请日：1995-11-02

Applicant: Satoru Yoshikawa ,  Tetsu Tanizawa

Inventor： Satoru Yoshikawa ,  Tetsu Tanizawa

IPC: G06G7/48 ,  G06F17/50 ,  G06T11/00

CPC classification number: G06F17/5022

Abstract: A method of verifying integrated circuit operation compares stored data structures which correspond to integrated circuit logic cells. Simulated graph data for a plurality of different types of logic cells are first determined by varying a plurality of factors including: the delay time of a logic cell after a signal is inputted until a signal is outputted, load capacity, and transient time of the inputted signal. The acquired graph data for each of the logic cells is then processed into data having a common origin at a common value and stored into a cell library. The processed graph data is then extracted as general-use graph data by comparing the acquired graph data with one another. A selector selects graph data which corresponds to an object of calculation from the library and an arithmetic logic unit calculates delay time of an actual logic cell based upon the selected graph data.

Abstract translation: 验证集成电路操作的方法与存储的与集成电路逻辑单元相对应的数据结构进行比较。 首先通过改变多个因素来确定多个不同类型的逻辑单元的模拟图形数据，包括：输入信号之后的逻辑单元的延迟时间，直到输出信号，负载容量和输入的瞬时时间 信号。 然后将每个逻辑单元的获取的图形数据以公共值处理成具有公共原点的数据并存储到单元库中。 然后通过将所获取的图形数据彼此进行比较来提取经处理的图形数据作为通用图形数据。 选择器从库中选择对应于计算对象的图形数据，并且算术逻辑单元基于所选择的图形数据来计算实际逻辑单元的延迟时间。

公开(公告)号：US5475261A

公开(公告)日：1995-12-12

申请号：US164784

申请日：1993-12-10

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L21/60 ,  H01L23/04 ,  H01L23/057 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48 ,  H01L29/41

CPC classification number: H01L24/73 ,  H01L23/04 ,  H01L23/057 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/81 ,  H05K3/3415 ,  H05K3/3426 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K3/3421 ,  H05K3/3447 ,  Y02P70/613

Abstract: A semiconductor device includes a predetermined number of surface mount first lead pins (14), arranged around the periphery of the underside of a package (13) fitted with a chip (11). A predetermined number of second lead pins (22, 41), each having a specific function, are provided in a region near the center of the underside of the package (13) inside of the region populated with the first lead pins (14).

Abstract translation: 半导体器件包括预定数量的表面安装的第一引线引脚（14），其布置在装配有芯片（11）的封装（13）的下侧的周边周围。 每个具有特定功能的预定数量的第二引线引脚（22,41）设置在安装有第一引脚（14）的区域内部的封装（13）的下侧附近的区域中。

公开(公告)号：US5216302A

公开(公告)日：1993-06-01

申请号：US761458

申请日：1991-09-18

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H03H11/26 ,  H03L7/081

CPC classification number: H03L7/0805 ,  H03H11/265 ,  H03L7/0812

Abstract: A reference delay generator includes a delay unit having a plurality of delay elements which are cascaded and respectively have variable delay times. The delay unit receives a reference signal and generates a delayed signal which is a delayed version of the reference signal. A control part detects a phase difference between the reference signal and the delayed signal and generates a control signal which sets the phase difference to an integer multiple of 90.degree.. The control signal is applied to the delay elements, so that the delay times of the delay elements are changed on the basis of the control signal. The control signal is used for, for example, controlling a delay circuit which includes a plurality of delay elements identical to those of the delay unit.

公开(公告)号：US5149993A

公开(公告)日：1992-09-22

申请号：US599595

申请日：1990-10-11

Applicant: Hideo Kikuchi ,  Tetsu Tanizawa

Inventor： Hideo Kikuchi ,  Tetsu Tanizawa

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/27 ,  G11C17/12 ,  H01L21/66 ,  H01L21/82 ,  H01L23/528

CPC classification number: G01R31/318516 ,  G11C17/12 ,  H01L23/528 ,  G06F11/27 ,  H01L2924/0002

Abstract: A circuit arrangement of a semiconductor integrated circuit device includes logic cell arrays arranged into columns. Each of the logic cell arrays have a plurality of logic cells. Each of the logic cells have at least one monitor point. The circuit arrangement also includes select lines which carry select signals, each specifying a corresponding one of the logic cells arrays. Further, the circuit arrangement includes read lines carrying monitor signals showing logic states of monitor points of the logic cells. The select lines and the read lines are provided so that the total number of the select lines and read lines is less than the sum total of the number of the logic cell arrays and a maximum number of monitor points contained in one of the logic cell arrays. Switch elements connect the monitor points of the logic cells to the read lines in response to the select signals.

公开(公告)号：US4928164A

公开(公告)日：1990-05-22

申请号：US393037

申请日：1989-08-10

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/82 ,  H01L21/8238 ,  H01L23/52 ,  H01L23/535 ,  H01L27/00 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L23/535 ,  H01L27/11807 ,  H01L2924/0002

Abstract: A semiconductor chip circuit device includes cell arrays having pairs of an n-channel device formation region and a p-channel device formation region. Conductive power source lines are selectively formed between the pairs and are situated in grooves in the substrate. The conductive lines are selectively connected to impurity introduction regions in each formation region of each pair. An insulating layer is formed in the grooves over the conductive lines, and wirings selectively connect a plurality of pairs formed on the insulating layer.

Abstract translation: 半导体芯片电路器件包括具有n沟道器件形成区域和p沟道器件形成区域对的单元阵列。 导电电源线选择性地形成在成对之间并且位于基板中的凹槽中。 导电线选择性地连接到每对形成区域中的杂质导入区域。 在导线上的沟槽中形成绝缘层，并且布线选择性地连接形成在绝缘层上的多个对。

公开(公告)号：US4868630A

公开(公告)日：1989-09-19

申请号：US769800

申请日：1985-08-27

Applicant: Tetsu Tanizawa ,  Yoshiharu Mitono ,  Hitoshi Omichi

Inventor： Tetsu Tanizawa ,  Yoshiharu Mitono ,  Hitoshi Omichi

IPC: H01L23/528 ,  H01L27/118

CPC classification number: H01L27/11898 ,  H01L23/528 ,  H01L2924/0002

Abstract: A semiconductor integrated circuit including at least one conventional inner cell region and an outer cell region. The outer cell region comprising a plurality of outer cells. Each outer cell is comprised of circuit elements for achieving a predetermined logic function, in addition to circuit elements for achieving the conventional buffer function of an outer cell. Further, two or more adjacent outer cells are connected each other and act as an independent circuit so as to form a macro-cell.

Abstract translation: 一种半导体集成电路，包括至少一个常规内部单元区域和外部单元区域。 外细胞区域包括多个外细胞。 除了用于实现外部单元的常规缓冲功能的电路元件之外，每个外部单元包括用于实现预定逻辑功能的电路元件。 此外，两个或更多个相邻的外部单元彼此连接，并且用作独立的电路以形成宏单元。