公开(公告)号：US20160204198A1

公开(公告)日：2016-07-14

申请号：US15079399

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

公开(公告)号：US20150187773A1

公开(公告)日：2015-07-02

申请号：US14573021

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Abstract translation: 包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有介电层。 finFET的鳍片具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍在通过衬底上的电介质层的第一沟槽中的第一硅 - 锗缓冲器上。 p沟道finFET的鳍在通过衬底上的电介质层的第二沟槽中的第二硅 - 锗缓冲器上。 翅片延伸至介电层上方至少10纳米。 散热片通过外延生长在电介质层的沟槽中的硅 - 锗缓冲器上形成，随后CMP平坦化到介电层。 电介质层凹入以暴露翅片。 翅片可以同时或分开地形成。

公开(公告)号：US20150008532A1

公开(公告)日：2015-01-08

申请号：US14497729

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra

IPC: H01L29/45 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/78 ,  H01L29/7845

Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.

Abstract translation: 晶体管形成在沟道区域上具有栅极的半导体衬底中，与沟道区相邻的衬底中的源极/漏极延伸区域以及与源极/漏极延伸区域相邻的衬底中的源极/漏极区域。 在源极/漏极延伸区域和源极/漏极区域上形成硅化物，使得硅化物在源极/漏极延伸区域上具有第一厚度，并且在源极/漏极区域上具有第二厚度，其中第二厚度大于第一厚度 厚度。 源极/漏极延伸区上的硅化物降低晶体管串联电阻，从而提高晶体管性能，并且还可以在接触蚀刻期间保护源极/漏极延伸区域免受硅损耗和硅损坏。

公开(公告)号：US08906770B2

公开(公告)日：2014-12-09

申请号：US14059503

申请日：2013-10-22

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra

IPC: H01L21/266 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/762 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.

Abstract translation: 通过形成具有不同掺杂剂浓度的多个n型栅极区域和具有不同掺杂剂浓度的多个p型栅极区域，半导体结构中的栅极交叉扩散被大大减少或消除，使得具有最低掺杂剂浓度的n型栅极区域接触 具有最低掺杂剂浓度的p型栅极区域。

公开(公告)号：US12272739B2

公开(公告)日：2025-04-08

申请号：US17098689

申请日：2020-11-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L49/02

Abstract: In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way.

公开(公告)号：US20250081558A1

公开(公告)日：2025-03-06

申请号：US18458280

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure generally relates to a semiconductor device having a reduced height gate electrode layer. In an example, a semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, a doped source/drain region, and a dielectric layer. The gate dielectric layer is on a surface of the substrate. The gate electrode layer is on the gate dielectric layer. The doped source/drain region is in the substrate and has a metallurgical junction parallel to a plane coplanar with the surface of the substrate. The metallurgical junction extends to a first vertical distance from the surface of the substrate. The gate electrode layer has a top surface that is a second vertical distance away from the surface of the substrate. The second vertical distance is equal to or less than half of the first vertical distance. The dielectric layer is over the substrate and the gate electrode layer.

公开(公告)号：US11532758B2

公开(公告)日：2022-12-20

申请号：US16581044

申请日：2019-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/47

Abstract: A method includes forming first and second trenches in a semiconductor substrate. The method further includes filling the first and second trenches with polysilicon. The polysilicon is oppositely doped from the semiconductor substrate. A Schottky contact is formed on the semiconductor substrate between the first and second trenches. The method also includes forming an anode for the Schottky contact. The anode is coupled to the polysilicon in the first and second trenches.

公开(公告)号：US10163725B2

公开(公告)日：2018-12-25

申请号：US15292373

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L27/092 ,  H01L27/11 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US09960162B2

公开(公告)日：2018-05-01

申请号：US15184405

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

公开(公告)号：US09805986B2

公开(公告)日：2017-10-31

申请号：US15079414

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L21/84 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.