公开(公告)号：US20080116524A1

公开(公告)日：2008-05-22

申请号：US12018851

申请日：2008-01-24

申请人： Xiangdong Chen ,  Haining Yang

发明人： Xiangdong Chen ,  Haining Yang

IPC分类号： H01L27/08

CPC分类号： H01L21/823807 ,  H01L29/7842

摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。 第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。 第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。 第二个值与第一个值大不相同。 此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

公开(公告)号：US20080111162A1

公开(公告)日：2008-05-15

申请号：US11559571

申请日：2006-11-14

申请人： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/04 ,  H01L21/311

CPC分类号： H01L21/30608 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7853

摘要： The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

摘要翻译： 本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。 通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。 或者，可以利用选择性外延生成新的面。 如此形成的小面被连接以在横截面中形成λ形轮廓。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

公开(公告)号：US20080099845A1

公开(公告)日：2008-05-01

申请号：US11552641

申请日：2006-10-25

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/8238

CPC分类号： H01L21/28123 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L29/66583 ,  H01L29/78

摘要： A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个晶体管的半导体结构，其中所述至少一个晶体管具有亚光刻沟道长度。 还提供了使用可以使用预制的硬掩模图案放置在特定位置的自组装嵌段共聚物来形成这种半导体结构的方法。

公开(公告)号：US20080050881A1

公开(公告)日：2008-02-28

申请号：US11931341

申请日：2007-10-31

申请人： Xiangdong Chen ,  Haining Yang

发明人： Xiangdong Chen ,  Haining Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TFET时，漏极区包括p掺杂的硅，而源区包括n掺杂的碳化硅。

公开(公告)号：US20080003735A1

公开(公告)日：2008-01-03

申请号：US11854829

申请日：2007-09-13

申请人： An STEEGEN ,  Haining Yang ,  Ying Zhang

发明人： An STEEGEN ,  Haining Yang ,  Ying Zhang

IPC分类号： H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

公开(公告)号：US20070259489A1

公开(公告)日：2007-11-08

申请号：US11879065

申请日：2007-07-16

申请人： Haining Yang ,  Huilong Zhu

发明人： Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654

摘要： A method of fabrication is provided in which a field effect transistor (FET) is formed having a channel region and source and drain regions adjacent to the channel region. A first stressed region underlies the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

摘要翻译： 提供一种制造方法，其中形成具有沟道区的场效应晶体管（FET）以及与沟道区相邻的源极和漏极区。 第一应力区域位于通道区域的下面，其中第一类型的应力是压缩型或拉伸型。 具有第二类型应力的第二应力区域位于源极和漏极区域之下，其中第二类型的应力是与第一应力区域的压缩类型或拉伸应力相反的一个。

公开(公告)号：US20070249174A1

公开(公告)日：2007-10-25

申请号：US11379634

申请日：2006-04-21

申请人： Haining Yang

发明人： Haining Yang

IPC分类号： H01L21/302

CPC分类号： H01L21/0337 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S977/887

摘要： A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.

摘要翻译： 处理装置的基板的方法包括以下步骤。 在基材上形成盖层。 在盖层上形成虚设层，盖层具有顶表面。 蚀刻虚拟层，形成具有可变宽度的图案化虚拟元件，并暴露虚拟元件的侧壁和除了虚拟元件之外的顶盖表面的部分。 在覆盖图案化的虚拟元件和盖层的暴露表面的器件上沉积间隔层。 将形成侧壁间隔物的间隔层向后蚀刻，除了图案化的虚设元件的侧壁之间间隔开最小间距之外，并且在图案化的虚设元件的侧壁之间形成超宽间隔物，其间隔小于最小间距。 剥去图案的虚拟元素。 将侧衬垫的一部分露出。 通过蚀刻到衬底中的衬底的图案曝光部分。

公开(公告)号：US20060172500A1

公开(公告)日：2006-08-03

申请号：US10906054

申请日：2005-02-01

申请人： Haining Yang ,  Huilong Zhu

发明人： Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  Y10S257/90

摘要： A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

摘要翻译： 半导体器件设置有应力沟道区域，其中引起应力沟道区域中的应力的应力膜可以部分地或全部地延伸在半导体器件的栅极结构之下。 在一些实施例中，应力膜环围绕通道区域，并且可以施加来自通道的所有侧面的应力。 因此，应力膜更好地围绕半导体器件的沟道区域并且可以在沟道区域中施加更多的应力。

公开(公告)号：US20060151833A1

公开(公告)日：2006-07-13

申请号：US10905586

申请日：2005-01-12

申请人： Haining Yang ,  Huilong Zhu

发明人： Haining Yang ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654

摘要： An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress are provided to underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

摘要翻译： 提供一种集成电路和制造方法，其中集成电路包括具有沟道区的场效应晶体管（FET）和与沟道区相邻的源极和漏极区。 提供具有第一类型应力的第一应力区域作为通道区域的下面，其中第一类型的应力是压缩型或拉伸型。 第二应力区域具有第二类型的应力，位于源区和漏区之下，其中第二类应力是与第一应力区的压缩类型或拉伸应力相反的一个。

公开(公告)号：US20060099793A1

公开(公告)日：2006-05-11

申请号：US10904059

申请日：2004-10-21

申请人： Haining Yang ,  Clement Wann ,  Huilong Zhu

发明人： Haining Yang ,  Clement Wann ,  Huilong Zhu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and only partially over the current-conducting member to expose a contact portion of the member. A first contact via is provided in conductive communication with the contact portion of the member, the first contact via having a self-aligned silicide-containing region. A second contact via is provided in conductive communication with the second portion of the semiconductor device region, the second contact via extending through the first film.

摘要翻译： 提供一种结构，其包括包括第一部分和第二部分的半导体器件区域。 提供导电构件，其在第一部分上水平延伸，但不在第二部分上。 诸如应力赋予膜的第一膜在第二部分上延伸并且仅部分地在导电构件上方以暴露构件的接触部分。 第一接触通孔设置成与构件的接触部分导电连通，第一接触通孔具有自对准的含硅化物区域。 第二接触通孔设置成与半导体器件区域的第二部分导电连通，第二接触通孔延伸穿过第一膜。