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31 条记录 (耗时 0.031 秒)

    Single-chip microcomputer
    21.
    发明授权
    Single-chip microcomputer 失效
    单片机

    公开(公告)号：US5428808A

    公开(公告)日：1995-06-27

    申请号：US217826

    申请日：1994-03-25

    申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F15/78 ,  G06F9/06

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

    摘要翻译： 内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

    Memory driving method
    25.
    发明授权
    Memory driving method 失效
    内存驱动方式

    公开(公告)号：US4308596A

    公开(公告)日：1981-12-29

    申请号：US81890

    申请日：1979-10-04

    申请人： Atsushi Takai ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Terumi Sawase ,  Takaaki Hagiwara

    发明人： Atsushi Takai ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Terumi Sawase ,  Takaaki Hagiwara

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/40 ,  G11C13/00

    CPC分类号： G11C16/26 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10

    摘要： In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.

    摘要翻译： 在每个具有至少栅极，衬底，源极和漏极的存储器单元的存储器阵列中，当衬底和源极和漏极处于相同的电位时，当存在电位差Vp时，进行写入操作 衬底和源极和漏极以及栅极处的电位。 当门和衬底之间存在电位差Vp时，存储的内容被擦除。 当存在基板和栅极之间的电位差Vp以及基板与源极和漏极之间存在电势差Vwd时，防止存储条件发生变化。 当这样的存储器阵列被部分地擦除时，通过在源极和漏极之间施加电压Vwd和电池的衬底之间施加电压V p来在单元的栅极和衬底之间施加电压V p来顺序地驱动不被擦除的单元， 对基板和电池栅极具有相同的电位。

    Microcomputer having a PROM including data security and test circuitry
    26.
    发明授权
    Microcomputer having a PROM including data security and test circuitry 失效
    具有PROM的微型计算机，包括数据安全和测试电路

    公开(公告)号：US5175840A

    公开(公告)日：1992-12-29

    申请号：US726113

    申请日：1991-06-21

    申请人： Terumi Sawase ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Toshimasa Kihara ,  Kiyoshi Matsubara ,  Tadashi Yamaura

    发明人： Terumi Sawase ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Toshimasa Kihara ,  Kiyoshi Matsubara ,  Tadashi Yamaura

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1433

    摘要： Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security. The first inhibition circuit is coupled to the data bus and provides a first inhibition operation to prevent access operations to the memory. The first inhibition circuit release the first inhibiting operation in accordance with a signal from outside the semiconductor substrate or body. The second inhibition means is coupled to the data bus and provides a second inhibiting operation to prevent access operations to the memory from outside the semiconductor body via the data bus and permanently disables the access operations to the memory irrespective of a releasing or termination of the first inhibiting operation after the second inhibiting operation has taken effect.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）的易测试性和数据安全性可以通过设置焊盘和输入/输出（I / O）电路来实现，该电路提供半导体衬底上的EEPROM测试所需的地址，数据和控制信号， 通过在基板上布置由EEPROM器件组成的两级测试I / O截取电路，使得一旦完成测试，由于具有内置的数据安全功能，防止了对半导体衬底之外的非法存取。 具有这种能力的微型计算机设置有用于处理数据的中央处理单元（CPU），诸如EEPROM的存储器，其通过公共总线（其传送数据，地址和控制信号）与CPU进行内部通信，其他 比在测试模式期间以及提供安全性的第一和第二抑制电路。 第一禁止电路耦合到数据总线，并提供第一禁止操作以防止对存储器的访问操作。 第一抑制电路根据来自半导体衬底或主体外部的信号来释放第一禁止操作。 第二禁止装置耦合到数据总线，并且提供第二禁止操作，以防止经由数据总线从半导体主体外部对存储器的访问操作，并且永久地禁用对存储器的访问操作，而不管第一 第二禁止操作之后的禁止操作已经起作用。

    High speed digital signal processor capable of achieving realtime operation
    28.
    发明授权
    High speed digital signal processor capable of achieving realtime operation 失效
    能实现实时操作的高速数字信号处理器

    公开(公告)号：US4945506A

    公开(公告)日：1990-07-31

    申请号：US324830

    申请日：1989-03-17

    申请人： Toru Baji ,  Hirotsugu Kojima ,  Nario Sumi ,  Yoshimune Hagiwara ,  Shinya Ohba

    发明人： Toru Baji ,  Hirotsugu Kojima ,  Nario Sumi ,  Yoshimune Hagiwara ,  Shinya Ohba

    IPC分类号： G06F17/10 ,  G06F17/16

    CPC分类号： G06F17/16

    摘要： A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).

    摘要翻译： 一种数字信号处理器，用于在包括多个数据项（x0，x1，x2，...，x7）的列向量输入信号和包括预定数量的系数数据项的矩阵之间计算矢量积，以便产生 列向量输出信号包括多个数据项（y0，y1，y2，...，y7）。 在第一周期中，列向量输入信号的前导数据x0存储在第一存储单元（Rin）中，而在该时间段内，在比第一周期更短的第二周期中，数据项（c0 顺序地读取构成矩阵的第一部分的行方向的c1，c1，c2，...，c7），使得两个数据项被相乘，从而将乘法结果存储在累加器中。 重复执行类似的数据处理，以便基于来自累加器的输出，获得由多个数据项（y0，y1，y2，...，y7）构成的列向量输出信号。