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    SEMICONDUCTOR MEMORY DEVICE
    23.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210036053A1

    公开(公告)日：2021-02-04

    申请号：US17074643

    申请日：2020-10-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Hung-Chan Lin ,  Jing-Yin Jhang ,  Yu-Ping Wang

    IPC: H01L27/22 ,  G11C11/16 ,  H01L23/48 ,  H01L43/12 ,  H01L23/544 ,  H01L21/321 ,  H01L21/762 ,  H01L23/485

    Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    24.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20210020832A1

    公开(公告)日：2021-01-21

    申请号：US17064606

    申请日：2020-10-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Yu-Ping Wang

    IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

    Method of forming semiconductor device
    26.
    发明授权
    Method of forming semiconductor device 有权

    公开(公告)号：US10608045B2

    公开(公告)日：2020-03-31

    申请号：US16297698

    申请日：2019-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Yu-Ping Wang

    IPC: H01L27/22 ,  H01L23/522 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16

    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.

    Semiconductor device and method of forming the same
    29.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09524967B1

    公开(公告)日：2016-12-20

    申请号：US15046458

    申请日：2016-02-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hao-Yeh Liu ,  Chien-Ming Lai ,  Yu-Ping Wang ,  Mon-Sen Lin ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu

    IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

    CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092

    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.

    Abstract translation: 半导体器件及其形成方法，所述半导体器件包括基板，以及全部设置在所述基板上的第一晶体管，第二晶体管和第三晶体管。 第一晶体管包括第一通道，以及在第一通道上彼此堆叠的第一势垒层和第一功函数层。 第二晶体管包括第二通道，以及彼此堆叠的第二阻挡层和第二功能层。 第三晶体管包括在第三沟道上彼此堆叠的第三沟道和第三势垒层和第三功函数层，其中第一势垒层，第二阻挡层和第三势垒层具有不同的氮比。 第一，第二和第三晶体管分别具有不同的阈值电压。

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