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    Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices
    21.
    发明授权
    Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices 有权
    在电子器件中形成电场的方法，钝化位错和点缺陷，提高光器件的发光效率

    公开(公告)号：US08114717B2

    公开(公告)日：2012-02-14

    申请号：US11599874

    申请日：2006-11-15

    Applicant: Tomas Palacios ,  Likun Shen ,  Umesh K. Mishra

    Inventor： Tomas Palacios ,  Likun Shen ,  Umesh K. Mishra

    IPC: H01L21/335

    CPC classification number: H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/0095

    Abstract: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.

    Abstract translation: 公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。 还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。 该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。 在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。 在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。 描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低 在关闭栅极的区域中的AlGaN覆盖层的厚度。

    METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS
    22.
    发明申请
    METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS 失效
    使用低温波形与Si（Ge）至III-N材料的异相结合制造晶体管的方法

    公开(公告)号：US20110169050A1

    公开(公告)日：2011-07-14

    申请号：US13069725

    申请日：2011-03-23

    Applicant: Umesh K. Mishra ,  Lee S. McCarthy

    Inventor： Umesh K. Mishra ,  Lee S. McCarthy

    IPC: H01L29/72 ,  H01L29/267 ,  H01L29/772

    CPC classification number: H01L29/7802 ,  H01L21/187 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7371 ,  H01L29/7786

    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

    Abstract translation: 一种制造电子器件的方法，包括在低于550℃的温度下将第一半导体材料晶体结合到III族氮化物半导体，以在第一半导体材料和III族氮化物半导体之间形成器件质量异质结，其中 第一半导体材料与III族氮化物半导体不同，并且与III族氮化物半导体相比被选择用于喷射器区域中的优异性能或优选的集成或制造特性。

    FABRICATION OF SINGLE OR MULTIPLE GATE FIELD PLATES
    23.
    发明申请
    FABRICATION OF SINGLE OR MULTIPLE GATE FIELD PLATES 审中-公开
    单门或多门闸门板的制造

    公开(公告)号：US20110018062A1

    公开(公告)日：2011-01-27

    申请号：US12898341

    申请日：2010-10-05

    Applicant: Alessandro Chini ,  Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

    Inventor： Alessandro Chini ,  Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

    IPC: H01L21/3205 ,  H01L29/78

    CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/785

    Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.

    Abstract translation: 使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。 这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。 此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。 使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

    High efficiency LED with tunnel junction layer
    25.
    发明授权
    High efficiency LED with tunnel junction layer 有权
    高效LED隧道结层

    公开(公告)号：US07737451B2

    公开(公告)日：2010-06-15

    申请号：US11362472

    申请日：2006-02-23

    Applicant: James P. Ibbetson ,  Bernd P. Keller ,  Umesh K. Mishra

    Inventor： James P. Ibbetson ,  Bernd P. Keller ,  Umesh K. Mishra

    IPC: H01L29/267

    CPC classification number: H01L33/04 ,  H01L33/0016 ,  H01L33/08 ,  H01L33/32

    Abstract: An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction.

    Abstract translation: 公开了一种由宽带隙半导体材料制成的LED，并具有在宽带隙半导体器件中具有隧道结的低电阻p型约束层。 不同的材料放置在材料产生天然偶极子的隧道结处。 该天然偶极子用于形成隧道宽度小于不具有不同材料的宽度的接合点。 在宽带隙半导体器件中具有隧道结的低电阻p型限制层可以通过在限制层的接合处产生极化电荷并在接合部中形成小于宽度的隧道宽度来制造 没有极化电荷。 可以通过在连接处添加杂质来增强通过限制层中的隧道结的隧穿。 这些杂质可能在结中形成带隙状态。

    GATED ELECTRODES FOR ELECTROLYSIS AND ELECTROSYNTHESIS
    27.
    发明申请
    GATED ELECTRODES FOR ELECTROLYSIS AND ELECTROSYNTHESIS 有权
    用于电解和电泳的电极

    公开(公告)号：US20080116080A1

    公开(公告)日：2008-05-22

    申请号：US11943363

    申请日：2007-11-20

    Applicant: Rakesh K. Lal ,  Likun Shen ,  Umesh K. Mishra

    Inventor： Rakesh K. Lal ,  Likun Shen ,  Umesh K. Mishra

    IPC: C25B1/00 ,  C25B11/00 ,  C25B9/00

    CPC classification number: C25B1/003 ,  C25B11/0447 ,  Y02P20/135

    Abstract: A gated electrode structure for altering a potential and electric field in an electrolyte near at least one working electrode is disclosed. The gated electrode structure may comprise a gate electrode biased appropriately with respect to a working electrode. Applying an appropriate static or dynamic (time varying) gate potential relative to the working electrode modifies the electric potential and field in an interfacial region between the working electrode and the electrolyte, and increases electron emission to and from states in the electrolyte, thereby facilitating an electrochemical, electrolytic or electrosynthetic reaction and reducing electrode overvoltage/overpotential.

    Abstract translation: 公开了一种用于改变靠近至少一个工作电极的电解质中的电场和电场的选通电极结构。 门电极结构可以包括相对于工作电极适当地偏置的栅电极。 施加相对于工作电极的适当的静态或动态（时变）门电位改变了工作电极和电解质之间的界面区域中的电位和场，并且增加了电解质中的电子发射，从而促进了 电化学，电解或电合成反应和还原电极过电压/超电势。

    Hemt structure with passivated donor layer
    29.
    发明授权
    Hemt structure with passivated donor layer 失效
    具有钝化施主层的Hemt结构

    公开(公告)号：US5172197A

    公开(公告)日：1992-12-15

    申请号：US812875

    申请日：1991-12-20

    Applicant: Loi D. Nguyen ,  Michael J. Delaney ,  Lawrence E. Larson ,  Umesh K. Mishra

    Inventor： Loi D. Nguyen ,  Michael J. Delaney ,  Lawrence E. Larson ,  Umesh K. Mishra

    IPC: H01L23/29 ,  H01L29/15 ,  H01L29/205 ,  H01L29/778

    CPC classification number: H01L29/155 ,  H01L23/291 ,  H01L29/205 ,  H01L29/7783 ,  H01L29/7787 ,  H01L2924/0002

    Abstract: A channel layer, donor layer, Schottky layer, and cap layer are formed on a substrate. A source and drain are formed on the cap layer. A gate is formed on the cap layer, or at the bottom of a recess which is formed through the cap layer and partially extends into the Schottky layer. The donor and Schottky layers are formed of a semiconductive material which includes an oxidizable component such as aluminum. A passivation or stop layer of a lattice-matched, non-oxidizable material is formed underlying the source, drain, and gate, and sealingly overlying the donor layer. The stop layer may be formed between the Schottky layer and the donor layer, or constitute a superlattice in combination with the Schottky layer consisting of alternating stop and Schottky sublayers. Alternatively, the stop layer may sealingly overlie the Schottky layer, and further constitute the cap layer.

    Abstract translation: 在衬底上形成沟道层，施主层，肖特基层和覆盖层。 在盖层上形成源极和漏极。 栅极形成在盖层上，或形成在通过盖层形成并部分延伸到肖特基层的凹部的底部。 供体和肖特基层由包括可氧化组分如铝的半导体材料形成。 晶格匹配的不可氧化材料的钝化或停止层形成在源极，漏极和栅极下方，并且密封地覆盖施主层。 阻挡层可以形成在肖特基层和施主层之间，或者构成与由交替停止和肖特基子层组成的肖特基层组合的超晶格。 或者，停止层可以密封地覆盖肖特基层，并进一步构成盖层。

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