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公开(公告)号：US09613969B2
公开(公告)日：2017-04-04
申请号：US14793714
申请日：2015-07-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC: H01L27/11 , H01L29/76 , H01L21/768 , H01L29/78 , H01L23/535 , H01L21/8234 , H01L21/311
CPC classification number: H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
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公开(公告)号：US20160351575A1
公开(公告)日：2016-12-01
申请号：US14793714
申请日：2015-07-07
Applicant: United Microelectronics Corp.
Inventor： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC: H01L27/11 , H01L21/768 , H01L21/8234 , H01L21/311 , H01L29/78 , H01L23/535
CPC classification number: H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
Abstract translation: 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。
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公开(公告)号：US20160306910A1
公开(公告)日：2016-10-20
申请号：US14690491
申请日：2015-04-20
Applicant: United Microelectronics Corp.
Inventor： Ting-Cheng Tseng , Ming-Jui Chen , Chia-Wei Huang
IPC: G06F17/50
CPC classification number: G06F17/5068 , G06F17/5081
Abstract: A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.
Abstract translation: 提供一种用于分解集成电路的布局的方法。 首先，导入集成电路的布局，其中布局包括单元区域中的多个子图案，并且在其上限定第一方向和第二方向。 接下来，将位于单元格区域的角落的一个子图案分配给锚图案。 然后，将与沿着第二方向的锚定图案相同的行中的子图案分配给第一组。 最后，根据设计规则，剩余的子图案被分解为第一组和第二组，其中同一行中的子图案被分解成第一组和第二组。
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公开(公告)号：US09274416B2
公开(公告)日：2016-03-01
申请号：US14023476
申请日：2013-09-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Ming-Jui Chen , Chia-Wei Huang , Hsin-Yu Chen , Kai-Lin Chuang
Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.
Abstract translation: 提供一种形成光掩模的方法。 提供与第一行相关的第一照片掩模图案，与第一通孔插头相关的原始第二照片掩模图案和与第二行相关的第三照片掩模图案。 执行第一光学邻近校正（OPC）处理。 执行第二OPC处理，包括沿着第一方向放大第二光掩模图案的宽度以形成修改的第二光刻胶图案。 执行轮廓模拟处理以确保修改的第二光掩模图案大于或等于原始第二掩模图案。 输出第一光掩模图案，修改的第二光掩模图案和第三光掩模图案。 本发明还提供一种OPC方法。
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公开(公告)号：US20150052491A1
公开(公告)日：2015-02-19
申请号：US13968391
申请日：2013-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Chao Tsao , Shih-Fang Hong , Chia-Wei Huang , Ming-Jui Chen , Shih-Fang Tzou , Ming-Te Wei
IPC: G06F17/50
CPC classification number: G06F17/5068 , G03F1/144 , G03F1/36
Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.
Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。
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Patent Agency Ranking
公开(公告)号：US20240162038A1
公开(公告)日：2024-05-16
申请号：US18167093
申请日：2023-02-10
Applicant: United Microelectronics Corp.
Inventor： Chien Heng Liu , Chia-Wei Huang , Yung-Feng Cheng , Ming-Jui Chen
IPC: H01L21/027 , G03F1/76
CPC classification number: H01L21/0271 , G03F1/76
Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.
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公开(公告)号：US20230317778A1
公开(公告)日：2023-10-05
申请号：US18206617
申请日：2023-06-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Heng Liu , Chia-Wei Huang , Hsin-Jen Yu , Yung-Feng Cheng , Ming-Jui Chen
IPC: H01L29/06 , H01L29/66 , H01L21/762 , H01L29/78
CPC classification number: H01L29/0649 , H01L29/66795 , H01L21/76224 , H01L29/7851
Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
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公开(公告)号：US10387602B2
公开(公告)日：2019-08-20
申请号：US15879788
申请日：2018-01-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tsung-Yeh Wu , Chia-Wei Huang , Yung-Feng Cheng
IPC: G06F17/50 , H01L21/02 , H01L21/033
Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
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公开(公告)号：US10026726B2
公开(公告)日：2018-07-17
申请号：US15604685
申请日：2017-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Chih-Sen Huang , Shih-Fang Tzou , Yi-Wei Chen , Yung-Feng Cheng , Li-Ping Huang , Chun-Hsien Huang , Chia-Wei Huang , Yu-Tse Kuo
IPC: H01L21/8238 , H01L21/768 , H01L27/11 , H01L29/78 , H01L29/66 , H01L27/092 , H01L27/02
Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
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公开(公告)号：US20170263597A1
公开(公告)日：2017-09-14
申请号：US15604685
申请日：2017-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Chih-Sen Huang , Shih-Fang Tzou , Yi-Wei Chen , Yung-Feng Cheng , Li-Ping Huang , Chun-Hsien Huang , Chia-Wei Huang , Yu-Tse Kuo
IPC: H01L27/02 , H01L21/8238 , H01L29/66 , H01L21/768 , H01L27/11 , H01L27/092
CPC classification number: H01L27/0207 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L21/823821 , H01L21/823871 , H01L27/0924 , H01L27/1104 , H01L29/66545 , H01L29/6681 , H01L29/7851
Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
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