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    METHOD OF FLATTENING A WAFER
    21.
    发明申请
    METHOD OF FLATTENING A WAFER 有权
    平铺方法

    公开(公告)号：US20150340222A1

    公开(公告)日：2015-11-26

    申请号：US14818293

    申请日：2015-08-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tai-Heng Yu ,  Chih-Yueh Li

    IPC: H01L21/02 ,  H01L21/308 ,  H01L21/306

    CPC classification number: H01L21/02021 ,  H01L21/02087 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/6708 ,  H01L21/68735

    Abstract: The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region.

    Abstract translation: 本发明的晶片斜面蚀刻装置包括用于覆盖晶片的部分的晶片保护掩模。 在晶片上限定了围绕中心区域的中心区域和晶片斜面区域。 晶片保护掩模包括中心遮蔽区域和至少一个晶片斜面遮蔽区域。 中心遮蔽区可以完全遮蔽晶片的中心区域，并且晶片斜面遮蔽区域从中心遮蔽区域的外边缘延伸，晶片斜面区域的遮蔽部分露出晶片斜面区域的其他部分。

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    23.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200185597A1

    公开(公告)日：2020-06-11

    申请号：US16216969

    申请日：2018-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

    TRAINING APPARATUS AND TRAINING METHOD FOR PROVIDING SAMPLE SIZE EXPANDING MODEL
    24.
    发明申请
    TRAINING APPARATUS AND TRAINING METHOD FOR PROVIDING SAMPLE SIZE EXPANDING MODEL 审中-公开

    公开(公告)号：US20200057966A1

    公开(公告)日：2020-02-20

    申请号：US16105182

    申请日：2018-08-20

    Applicant: United Microelectronics Corp.

    Inventor： Yao-Sheng Chang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Da-Ching Liao

    IPC: G06N99/00 ,  G06F5/01 ,  G06F17/16

    Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    26.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150380312A1

    公开(公告)日：2015-12-31

    申请号：US14314425

    申请日：2014-06-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L21/311

    CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂敷抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

    METHOD FOR REMOVING NITRIDE MATERIAL
    27.
    发明申请
    METHOD FOR REMOVING NITRIDE MATERIAL 有权
    去除氮化物的方法

    公开(公告)号：US20140256151A1

    公开(公告)日：2014-09-11

    申请号：US13784846

    申请日：2013-03-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chi-Sheng Chen ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Ted Ming-Lang Guo ,  Bo-Syuan Lee ,  Tsung-Hsun Tsai ,  Yu-Chin Cheng

    IPC: H01L21/308

    CPC classification number: H01L21/308 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.

    Abstract translation: 一种除去氮化硅材料的方法包括以下步骤。 提供了至少形成有栅极结构的衬底，并且在栅极结构的顶部上形成至少一个氮化硅硬掩模。 执行第一次去除以用第一磷酸（H 3 PO 4）溶液去除一部分氮化硅硬掩模。 随后进行第二次去除以用第二种磷酸溶液去除残留的氮化硅硬掩模。 第一次去除和第二次去除是原位进行的。 第二磷酸溶液的温度低于第一磷酸溶液的温度。

    Training apparatus and training method for providing sample size expanding model
    29.
    发明授权
    Training apparatus and training method for providing sample size expanding model 有权

    公开(公告)号：US11461693B2

    公开(公告)日：2022-10-04

    申请号：US16105182

    申请日：2018-08-20

    Applicant: United Microelectronics Corp.

    Inventor： Yao-Sheng Chang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Da-Ching Liao

    IPC: G06N20/00 ,  G06F17/16 ,  G06F5/01

    Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

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