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    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    22.
    发明申请
    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20150349088A1

    公开(公告)日：2015-12-03

    申请号：US14821815

    申请日：2015-08-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

    IPC: H01L29/66

    CPC classification number: H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

    Abstract translation: 半导体结构包括设置在基板上并具有外部间隔件的栅极结构，设置在基板中并与栅极结构相邻的凹槽，填充凹部的掺杂的外延材料，包括未掺杂的外延材料的盖层， 所述掺杂的外延材料是设置在所述覆盖层下方并且夹在所述掺杂的外延材料和所述覆盖层之间的轻掺杂漏极，以及设置在所述覆盖层上并覆盖所述掺杂外延材料以与所述外部间隔物一起覆盖所述覆盖层的硅化物 而不直接接触轻掺杂的漏极。

    METHOD FOR GENERATING LAYOUT PATTERN
    23.
    发明申请
    METHOD FOR GENERATING LAYOUT PATTERN 有权
    生成布局图案的方法

    公开(公告)号：US20150347657A1

    公开(公告)日：2015-12-03

    申请号：US14822907

    申请日：2015-08-11

    Applicant: United Microelectronics Corp.

    Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

    Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

    Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    27.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20150200192A1

    公开(公告)日：2015-07-16

    申请号：US14153079

    申请日：2014-01-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Yao-Hung Huang ,  Chien-Ting Lin ,  Ming-Te Wei

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/02

    CPC classification number: H01L27/0922 ,  H01L21/02164 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385

    Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

    Abstract translation: 本发明提供一种半导体结构，包括其上设置有介电层的基板，限定在其上的第一器件区域和第二器件区域，设置在第一器件区域内的衬底中的至少一个第一沟槽，至少一个第二 沟槽和设置在第二器件区域内的衬底中的至少一个第三沟槽，设置在第二沟槽和第三沟槽中的功函数层，其中功函数层部分地覆盖第二沟槽的侧壁，并且完全覆盖 第三沟槽的侧壁和设置在第二沟槽和第三沟槽中的第一材料层，其中第一材料层覆盖设置在第二沟槽的部分侧壁上的功函数层，并且完全覆盖设置在第二沟槽上的功函数层 第三沟槽的侧壁。

    METHOD FOR GENERATING LAYOUT PATTERN
    28.
    发明申请
    METHOD FOR GENERATING LAYOUT PATTERN 有权
    生成布局图案的方法

    公开(公告)号：US20150052491A1

    公开(公告)日：2015-02-19

    申请号：US13968391

    申请日：2013-08-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

    Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

    Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。

    Die Seal Ring and Method of Forming the Same
    29.
    发明申请
    Die Seal Ring and Method of Forming the Same 有权
    模具密封圈及其形成方法

    公开(公告)号：US20140367835A1

    公开(公告)日：2014-12-18

    申请号：US13921174

    申请日：2013-06-18

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Te Wei ,  Po-Chao Tsao ,  Ching-Li Yang ,  Chien-Yang Chen ,  Hui-Ling Chen ,  Guan-Kai Huang

    IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768

    CPC classification number: H01L23/562 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.

    Abstract translation: 提供了模具密封环。 模具密封环包括基材和从基材挤出的第一层。 第一层具有第一鳍环结构，并且第一鳍环结构的布局具有戳状形状。 此外，提供了一种用于形成模具密封环的方法。 提供具有有源区的衬底。 在衬底上形成图案化的牺牲层。 在图案化牺牲层的侧壁上形成间隔物。 图案化的牺牲层被去除。 通过使用间隔物作为掩模对衬底进行构图，从而同时形成Fin-FET的鳍结构和模密封环的第一层。

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