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    Method for generating layout pattern
    2.
    发明授权
    Method for generating layout pattern 有权
    生成布局模式的方法

    公开(公告)号：US09208276B1

    公开(公告)日：2015-12-08

    申请号：US14822907

    申请日：2015-08-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

    Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

    Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

    METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR
    3.
    发明申请
    METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR 有权
    制备金属氧化物半导体晶体管的方法

    公开(公告)号：US20140322883A1

    公开(公告)日：2014-10-30

    申请号：US14331229

    申请日：2014-07-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Te Wei ,  Wen-Chen Wu ,  Lung-En Kuo ,  Po-Chao Tsao

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66689 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

    Abstract translation: 公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

    Semiconductor structure and manufacturing method thereof
    8.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权
    半导体结构及其制造方法

    公开(公告)号：US09318490B2

    公开(公告)日：2016-04-19

    申请号：US14153079

    申请日：2014-01-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Yao-Hung Huang ,  Chien-Ting Lin ,  Ming-Te Wei

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/8234

    CPC classification number: H01L27/0922 ,  H01L21/02164 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385

    Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

    Abstract translation: 本发明提供一种半导体结构，包括其上设置有介电层的基板，限定在其上的第一器件区域和第二器件区域，设置在第一器件区域内的衬底中的至少一个第一沟槽，至少一个第二 沟槽和设置在第二器件区域内的衬底中的至少一个第三沟槽，设置在第二沟槽和第三沟槽中的功函数层，其中功函数层部分地覆盖第二沟槽的侧壁，并且完全覆盖 第三沟槽的侧壁和设置在第二沟槽和第三沟槽中的第一材料层，其中第一材料层覆盖设置在第二沟槽的部分侧壁上的功函数层，并且完全覆盖设置在第二沟槽上的功函数层 第三沟槽的侧壁。

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