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公开(公告)号：US20140063970A1
公开(公告)日：2014-03-06
申请号：US13902863
申请日：2013-05-27
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Lu-Ping Chiang
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C16/0483
Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE′ is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.
Abstract translation: 提供了利用小型化的感测电路执行高速读取的半导体存储器件。 当选择偶数位线时，来自虚拟电位VPRE'的预充电电压被提供给奇数位线，预充电电压从源电压提供单元230提供给共享奇数源极线SL_o，地 电源电压提供单元230提供给偶数源极线SL_e。
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公开(公告)号：US20240347106A1
公开(公告)日：2024-10-17
申请号：US18444730
申请日：2024-02-18
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C11/5642 , G11C11/54 , G11C11/5628
Abstract: A semiconductor device is capable of improving calculating ability and processing efficiency in AI learning and the like. A flash memory (100) includes a NAND-type or NOR-type memory cell array (110) and a calculation processing part (190). The calculation processing part (190) includes a bit line current detection part (200); a voltage holding part (210) holding a voltage corresponding to the detected current; an adding part (220) adding voltages held by the voltage holding part (210); and an A/D conversion part (230) performing A/D conversion on an addition result of the adding part (220). The calculation processing part (190) may calculate a sum of the current flowing in a bit line in a row direction and/or a column direction when the memory cell array is read.
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公开(公告)号：US12080353B2
公开(公告)日：2024-09-03
申请号：US17988782
申请日：2022-11-17
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Toshiaki Takeshita
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/3445
Abstract: The disclosure provides a semiconductor device and an erasing method that may alleviate the deterioration of a memory cell caused by ISPE. The NAND flash memory in the disclosure includes a memory cell array and an erasing component that erases selected blocks of the memory cell array. The erasing component performs a first erasing verification (EV1) and a second erasing verification (EV2) on the selected block. When the first erasing verification (EV1) passes, and the second erasing verification (EV2) fails, an erase pulse with the same erase voltage as the last time is applied, and when the first erasing verification (EV1) fails, an erase pulse with a step voltage higher than the last time is applied.
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公开(公告)号：US12073882B2
公开(公告)日：2024-08-27
申请号：US17975609
申请日：2022-10-28
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0038
Abstract: A semiconductor memory device capable of automatically restoring writing interrupted due to a momentary stop or a fluctuation of a power supply voltage is provided. A non-volatile memory of the disclosure includes a memory cell array formed with a NOR array and a variable resistance array. When the power supply voltage drops to a power-off level during writing into the NOR array, a reading/writing control unit writes unwritten data into the variable resistance array. Subsequently, when a power-on of the power supply voltage is detected, the reading/writing control unit reads the unwritten data from the variable resistance array and writes the unwritten data into the NOR array, so that interrupted writing is restored.
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公开(公告)号：US20240265964A1
公开(公告)日：2024-08-08
申请号：US18429450
申请日：2024-02-01
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Masato Ono , Takehiro Kaminaga
IPC: G11C11/56
CPC classification number: G11C11/56
Abstract: A flash memory that improves the reliability of data stored in a memory cell array is provided in the disclosure. A wear leveling method of the flash memory of the disclosure includes the following operation. The memory cell array includes multiple sectors, the method includes the following operation. A region is set for storing a first flag and a second flag in each sector of multiple sectors of the memory cell array. The first flag indicates whether bit correction has occurred, and the second flag indicates whether specific data is stored. The second flag of a source sector among the sectors in which the specific data is stored is set. The specific data is written to a new sector among the sectors in which the first flag is in a reset state, and the second flag of the new sector is set.
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Patent Agency Ranking
公开(公告)号：US12033681B2
公开(公告)日：2024-07-09
申请号：US17727834
申请日：2022-04-25
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
IPC: G11C11/00 , G11C13/00 , G11C16/04 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , H10B43/30 , H10B63/00
CPC classification number: G11C11/005 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C16/0466 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , H10B43/30 , H10B63/00
Abstract: A semiconductor storage device capable of achieving low power and high integration is provided. A non-volatile semiconductor memory of the disclosure includes a memory cell array. The memory cell array has a NOR array with a NOR flash memory structure and a variable resistance array with a variable resistance memory structure formed on a substrate. An entry gate is formed between the NOR array and the variable resistance array. When the NOR array is accessed, the entry gate separates the variable resistance array from the NOR array.
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公开(公告)号：US11798628B2
公开(公告)日：2023-10-24
申请号：US17462006
申请日：2021-08-31
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Toshiaki Takeshita
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/349 , G11C16/3459
Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.
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公开(公告)号：US11271005B2
公开(公告)日：2022-03-08
申请号：US16893411
申请日：2020-06-04
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Riichiro Shirota
IPC: H01L27/1157 , H01L27/11573 , H01L29/792 , H01L27/11582 , H01L21/28
Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.
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公开(公告)号：US20220013172A1
公开(公告)日：2022-01-13
申请号：US17367641
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.
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公开(公告)号：US20180261285A1
公开(公告)日：2018-09-13
申请号：US15861701
申请日：2018-01-04
Applicant: Winbond Electronics Corp.
Inventor： Norio Hattori , Masaru Yano
CPC classification number: G11C13/004 , G11C8/08 , G11C13/0023 , G11C13/0028 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C13/0097 , G11C2013/0047 , H01L27/24 , H01L2924/1438
Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.
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