公开(公告)号：US20240211138A1

公开(公告)日：2024-06-27

申请号：US18145339

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Ahmad R. Ansari

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

公开(公告)号：US11580057B2

公开(公告)日：2023-02-14

申请号：US16666262

申请日：2019-10-28

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F15/177 ,  G06F9/00 ,  G06F15/78 ,  G06F1/26 ,  G06F9/4401 ,  G06F11/07 ,  G06F21/57 ,  G06F21/60 ,  G06F21/71 ,  G06F21/76 ,  G06F21/86

Abstract: An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.

公开(公告)号：US20210124711A1

公开(公告)日：2021-04-29

申请号：US16666262

申请日：2019-10-28

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F15/78 ,  G06F21/57 ,  G06F21/76 ,  G06F1/26 ,  G06F21/71 ,  G06F21/60 ,  G06F21/86 ,  G06F9/4401 ,  G06F11/07

Abstract: An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.

公开(公告)号：US10896119B1

公开(公告)日：2021-01-19

申请号：US16180811

申请日：2018-11-05

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari ,  Felix Burton ,  Henry C. Yu

IPC: G06F11/00 ,  G06F11/36 ,  G06F13/16 ,  G06F13/40 ,  G06F13/28 ,  G06F5/06

Abstract: An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.

公开(公告)号：US20190303268A1

公开(公告)日：2019-10-03

申请号：US15944137

申请日：2018-04-03

Applicant: Xilinx,Inc.

Inventor： Ahmad R. Ansari ,  Felix Burton ,  Ming-dong Chen

IPC: G06F11/36 ,  G01R31/317 ,  G06F17/50

Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

公开(公告)号：US09990131B2

公开(公告)日：2018-06-05

申请号：US14493081

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  James J. Murray ,  Nishit Patel ,  Ahmad R. Ansari

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/30

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/3004 ,  G06F13/1657 ,  G06F2003/0697

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

公开(公告)号：US09696789B2

公开(公告)日：2017-07-04

申请号：US14462492

申请日：2014-08-18

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Ahmad R. Ansari ,  Soren Brinkmann

IPC: G06F1/32 ,  G06F13/24

CPC classification number: G06F1/3287 ,  G06F1/3215 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/24 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

公开(公告)号：US20170168841A1

公开(公告)日：2017-06-15

申请号：US14969362

申请日：2015-12-15

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari

IPC: G06F9/44 ,  G06F11/263 ,  G06F15/78 ,  G06F11/22

CPC classification number: G06F9/4403 ,  G06F9/4401 ,  G06F11/2284 ,  G06F11/2635 ,  G06F15/781 ,  G06F2011/2278

Abstract: In an example, a system-on-chip (SoC) includes a hardware power-on-reset (POR) sequencer circuit coupled to a POR pin. The SoC further includes a platform management unit (PMU) circuit, coupled to the hardware POR sequencer circuit, the PMU including one or more central processing units (CPUs) and a read only memory (ROM). The SoC further includes one or more processing units configured to execute a boot process. The hardware POR sequencer circuit is configured to initialize the PMU. The one or more CPUs of the PMU are configured to execute code stored in the ROM to perform a pre-boot initialization.