公开(公告)号：US09831218B1

公开(公告)日：2017-11-28

申请号：US15480258

申请日：2017-04-05

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Michael J. Hart

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/60 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06572

Abstract: Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a stacked IC device is provided that includes a first wafer, a second wafer, and first conductive bridge. The second wafer is stacked on and secured to the first wafer. The second wafer has a plurality of IC dice that are communicatively coupled to a plurality of IC dice formed on the first wafer. The first conductive bridge has a first end that is sandwiched between the first and second wafers. The first conductive bridge shorts exposed pads of dice formed in the exclusion zones of the first and second wafers.

公开(公告)号：US09013844B2

公开(公告)日：2015-04-21

申请号：US13741619

申请日：2013-01-15

Applicant: Xilinx, Inc.

Inventor： James Karp

IPC: H02H9/04 ,  H01L27/06 ,  H01L27/02

CPC classification number: H02H9/044 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0629

Abstract: A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described.

Abstract translation: 描述了用于使能集成电路中的电荷放电的电路。 该电路包括耦合到第一节点的输入/输出垫; 耦合在第一节点和接地节点之间的第一二极管; 与所述第一节点和所述接地节点之间的所述第一二极管并联耦合的晶体管; 以及耦合在晶体管的主体部分和接地节点之间的电阻器。 还描述了能够进行电荷放电的方法。

公开(公告)号：US20140145293A1

公开(公告)日：2014-05-29

申请号：US13686553

申请日：2012-11-27

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  James Karp ,  Michael J. Hart

IPC: H01L23/552 ,  H01L21/02

CPC classification number: H01L23/552 ,  G11C11/4125 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract translation: 描述了具有改善的辐射抗扰性的集成电路。 集成电路包括基板; 在衬底上形成的P阱，并具有存储单元的N型晶体管; 和形成在衬底上并具有存储单元的P型晶体管的N阱; 其中所述N阱具有用于容纳所述P型晶体管的最小尺寸。

公开(公告)号：US11043484B1

公开(公告)日：2021-06-22

申请号：US16362134

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  James Karp ,  Siow Chek Tan ,  Martin L. Voogel ,  Mohsen H. Mardi ,  Suresh Ramalingam ,  David M. Mahoney

IPC: H01L27/02 ,  G01R1/04 ,  H01L25/065 ,  H01L23/498

Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

公开(公告)号：US10861848B2

公开(公告)日：2020-12-08

申请号：US16110894

申请日：2018-08-23

Applicant: Xilinx, Inc.

Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

IPC: H01L27/06 ,  H01L27/02 ,  H01L49/02 ,  H01L29/73 ,  H01L29/78

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

公开(公告)号：US20200066837A1

公开(公告)日：2020-02-27

申请号：US16109273

申请日：2018-08-22

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Michael J. Hart

IPC: H01L29/06 ,  H01L27/06 ,  H01L27/092

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

公开(公告)号：US10522531B1

公开(公告)日：2019-12-31

申请号：US16154647

申请日：2018-10-08

Applicant: Xilinx, Inc.

Inventor： James Karp

IPC: H01L27/02 ,  G02B6/42 ,  H04B10/80 ,  H01L23/60 ,  H04B10/60 ,  H04B10/50 ,  H04B10/40

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.

公开(公告)号：US09483599B1

公开(公告)日：2016-11-01

申请号：US14494361

申请日：2014-09-23

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  James Karp

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5022 ,  G06F17/5054 ,  G06F17/5081

Abstract: Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.

Abstract translation: 确定电路设计特定的集成电路（IC）的单事件故障的时间速率失败包括使用处理器确定用于目标IC的电路设计的多个关键互连多路复用器位，并确定关键的数量 查找表位用于电路设计。 使用处理器，使用关键互连复用器位数和关键查找表位数来估计目标IC的电路设计的设备漏洞因素。 可以存储估计的设备脆弱性因子，例如用于随后与其他电路设计的比较。

公开(公告)号：US20160293548A1

公开(公告)日：2016-10-06

申请号：US14674321

申请日：2015-03-31

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Vassili Kireev

IPC: H01L23/538 ,  H01L27/02

CPC classification number: H01L23/5382 ,  H01L23/3121 ,  H01L23/5386 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107 ,  H03K19/1732 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

Abstract translation: 各种示例性实现涉及用于多芯片集成电路（IC）封装上的管芯间通信的电路和方法。 根据示例实现，IC封装包括具有用于在封装的各个数据端子上传送数据的多个通信电路的第一半导体管芯。 封装还包括具有N个触点的第二半导体管芯，用于将数据传送到半导体管芯和从半导体管芯传送数据。 第二半导体管芯包括被配置为将M个并行数据信号与封装的一个或多个其它半导体管芯通信的逻辑电路，其中M> N。 第二半导体裸片还包括多个串行化器电路，每个串行器电路被配置为串行化来自多个M个信号线的相应子集的数据，以产生串行数据并将序列化数据提供给相应的一个触点。

公开(公告)号：US09378322B1

公开(公告)日：2016-06-28

申请号：US14603946

申请日：2015-01-23

Applicant: Xilinx, Inc.

Inventor： James Karp

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: According to a method of preparing a layout of semiconductor circuit elements, a computer processor determines a first value of a distance metric that describes a separation between at least one well of a first type and at least one well of a second type in a first layout of a circuit design represented in a memory coupled to the computer processor. The at least one well of the first type and the at least one well of the second type are rearranged into a second layout. The method determines a second value of the distance metric that describes separation between the at least one well of the first type and the at least one well of the second type in the second layout. The second layout is stored in response to the second value of the distance metric being greater than the first value of the distance metric.

Abstract translation: 根据制备半导体电路元件的布局的方法，计算机处理器确定在第一布局中描述第一类型的至少一个阱和第二类型的至少一个阱之间的间隔的距离度量的第一值 表示在耦合到计算机处理器的存储器中的电路设计。 第一类型的至少一个井和第二类型的至少一个井重新排列成第二布局。 所述方法确定所述距离度量的第二值，所述第二值描述在所述第二布局中所述第一类型的所述至少一个井和所述第二类型的所述至少一个井之间的间隔。 响应于距离度量的第二值大于距离度量的第一值来存储第二布局。