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公开(公告)号:US11302674B2
公开(公告)日:2022-04-12
申请号:US16880811
申请日:2020-05-21
Applicant: XILINX, INC.
Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam , William E. Allaire , Hong Shi , Kerry M. Pierce
IPC: H01L25/065 , H01L23/00 , H01L25/00
Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.
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公开(公告)号:US11246211B1
公开(公告)日:2022-02-08
申请号:US17188795
申请日:2021-03-01
Applicant: XILINX, INC.
Inventor: Gamal Refai-Ahmed , Nagadeven Karunakaran , Hoa Do , Suresh Ramalingam
IPC: H05K1/02
Abstract: Micro devices having enhanced through printed circuit board (PCB) heat transfer are provided. In one example, a micro device is provided that includes a PCB, a thermal management device, a chip package, a bracket, and a plurality of extra-package heat conductors. The chip package has a first side facing the thermal management device and a second side mounted to a first side of the PCB. The bracket is disposed on a second side of the PCB that faces away from the chip package. The plurality of extra-package heat conductors are disposed laterally outward of the chip package and provide at least a portion of a thermally conductive heat transfer path between the bracket and the thermal management device through the PCB.
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公开(公告)号:US11217550B2
公开(公告)日:2022-01-04
申请号:US16044363
申请日:2018-07-24
Applicant: Xilinx, Inc.
Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam
IPC: H01L23/00 , H01L21/3065 , H01L21/78
Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.
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24.
公开(公告)号:US10720377B2
公开(公告)日:2020-07-21
申请号:US16186178
申请日:2018-11-09
Applicant: Xilinx, Inc.
Inventor: Gamal Refai-Ahmed , Ho Hyung Lee , Hui-Wen Lin , Henley Liu , Suresh Ramalingam
IPC: H01L29/40 , H01L23/40 , H01L23/48 , H01L23/00 , H01L23/427
Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.
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25.
公开(公告)号:US20200035635A1
公开(公告)日:2020-01-30
申请号:US16044363
申请日:2018-07-24
Applicant: Xilinx, Inc.
Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam
IPC: H01L23/00 , H01L21/3065 , H01L21/78
Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.
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公开(公告)号:US10319606B1
公开(公告)日:2019-06-11
申请号:US15813008
申请日:2017-11-14
Applicant: Xilinx, Inc.
Inventor: Jaspreet Singh Gandhi , Tien-Yu Lee , Henley Liu , Ivor G. Barber , Suresh Ramalingam
Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.
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公开(公告)号:US10043730B2
公开(公告)日:2018-08-07
申请号:US14867349
申请日:2015-09-28
Applicant: Xilinx, Inc.
Inventor: Gamal Refai-Ahmed , Tien-Yu Lee , Ferdinand F. Fernandez , Suresh Ramalingam , Ivor G. Barber , Inderjit Singh , Nael Zohni
IPC: H01L23/10 , H01L23/367 , H01L25/065 , H01L23/373 , H01L25/00 , H01L23/16 , H01L25/18 , H01L23/04 , H01L23/473 , H01L21/48 , H01L23/00 , H01L23/40
Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.
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公开(公告)号:US12027493B2
公开(公告)日:2024-07-02
申请号:US16672802
申请日:2019-11-04
Applicant: XILINX, INC.
Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam
IPC: H01L25/065 , H01L21/56 , H01L21/60 , H01L23/00
CPC classification number: H01L25/0655 , H01L21/565 , H01L24/05 , H01L2021/60007 , H01L2224/02371 , H01L2224/02372
Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.
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公开(公告)号:US11605886B1
公开(公告)日:2023-03-14
申请号:US17133518
申请日:2020-12-23
Applicant: XILINX, INC.
Inventor: Gamal Refai-Ahmed , Chi-Yi Chao , Lik Tsang , Jens Weis , Brendan Farley , Anthony Torza , Suresh Ramalingam
IPC: H01Q1/42 , H01L23/427 , H01Q1/02
Abstract: An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.
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公开(公告)号:US11488936B2
公开(公告)日:2022-11-01
申请号:US16718868
申请日:2019-12-18
Applicant: Xilinx, Inc.
Inventor: Gamal Refai-Ahmed , Suresh Ramalingam , Jaspreet Singh Gandhi , Cheang-Whang Chang
IPC: H01L25/065 , H01L23/367 , H01L23/04 , H01L23/31
Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.
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