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公开(公告)号：US20080177855A1
公开(公告)日：2008-07-24
申请号：US12076686
申请日：2008-03-21
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L69/161 , H04L69/162 , H04L69/22
摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.
摘要翻译： 包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在 受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。 复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少 加载CPU并增加通信处理速度。
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22.发明授权Information processor and information processing system utilizing clock signal 失效信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5974560A
公开(公告)日：1999-10-26
申请号：US788831
申请日：1997-01-27
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。
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23.发明授权Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US5133064A
公开(公告)日：1992-07-21
申请号：US184782
申请日：1988-04-22
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。
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公开(公告)号：US08645022B2
公开(公告)日：2014-02-04
申请号：US12575212
申请日：2009-10-07
申请人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
发明人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
CPC分类号： B60W30/00 , B60K6/46 , B60K6/52 , B60L3/0023 , B60L3/003 , B60L3/0076 , B60L3/0092 , B60L15/2009 , B60L2240/12 , B60L2240/20 , B60L2240/24 , B60L2240/423 , B60L2250/26 , B60T7/12 , B60W10/04 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/18 , B60W10/20 , B60W20/00 , B60W40/08 , B60W40/10 , B60W50/02 , B60W50/0225 , B60W50/04 , B60W2510/20 , B60W2510/202 , B60W2520/14 , B60W2540/10 , B60W2540/12 , B60W2550/20 , B62D5/046 , B62D5/0481 , B62D6/00 , G06F11/0796 , Y02T10/6217 , Y02T10/6265 , Y02T10/6286 , Y02T10/645 , Y02T10/72 , Y02T10/7275 , Y02T90/16
摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.
摘要翻译： 一种车辆控制系统，可以通过简化的ECU配置和低成本确保高可靠性，实时处理和可扩展性，通过整个系统中的协调备份错误，而不会增加单个控制器的冗余程度，超出最不必要的范围 水平。 车辆控制系统包括：传感器控制器，用于接收指示车辆的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器，用于基于由传感器控制器接收的传感器信号产生控制目标值; 以及致动器控制器，用于从命令控制器接收控制目标值并操作致动器来控制车辆，这三个控制器经由网络互连。 执行器控制器包括控制目标值产生单元，用于当由指令控制器产生的控制目标值异常时，基于由传感器控制器接收并由致动器控制器经由网络接收的传感器信号产生控制目标值;以及 根据由控制目标值产生单元产生的控制目标值来控制致动器。
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公开(公告)号：US07557809B2
公开(公告)日：2009-07-07
申请号：US10983757
申请日：2004-11-09
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
IPC分类号： G06F13/14 , G09G5/39 , G06F15/167
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
摘要翻译： 多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。 在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。 与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。 统一的存储器端口可以比系统总线更快地驱动。
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公开(公告)号：US07496679B2
公开(公告)日：2009-02-24
申请号：US10446929
申请日：2003-05-29
IPC分类号： G06F15/16
摘要： A packet communication apparatus capable of performing packet conversion at high speed for packet transfer or packet transmission/reception has: a packet conversion unit for performing packet conversion for a reception packet received at a plurality of communication units and for a transmission packet to be transmitted from the plurality of communication units; and a transfer control unit for outputting, when the reception packet received by the communication unit is judged as a the transfer packet, the reception packet to a transfer buffer, for outputting the transmission packet to the communication unit corresponding to the communication object at a destination of the transmission packet generated by a packet generating and processing unit, and for outputting the transfer packet to the communication unit corresponding to the communication object at a destination of the transfer packet stored in the transfer buffer.
摘要翻译： 能够高速进行分组转换以进行分组传送或分组发送/接收的分组通信装置具有：分组转换单元，用于对在多个通信单元接收的接收分组进行分组转换，以及对于要从 所述多个通信单元; 以及传送控制单元，用于当将由通信单元接收到的接收分组判断为传送分组时，将接收分组输出到传送缓冲器，用于将发送分组输出到与目的地的通信对象相对应的通信单元 由分组产生和处理单元产生的传输分组，并且用于将存储在传送缓冲器中的传送分组的目的地处的传送分组输出到与通信对象对应的通信单元。
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公开(公告)号：US20060064546A1
公开(公告)日：2006-03-23
申请号：US11190004
申请日：2005-07-27
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/3824
摘要： [Problem] To provide a microprocessor in which the bottleneck due to data sharing during memory access when a CPU and a plurality of accelerators are operated in a linked up manner can be minimized, whereby enhanced multimedia processing performance can be achieved. [Means for solving the problem] A multimedia microprocessor 1 includes a CPU 11 and accelerators 12 in which the CPU 11 and the accelerators 12 perform multimedia processing in a linked up manner. In order to prevent the bottleneck caused by data sharing during memory access between the CPU 11 and the accelerators 12 via a memory 2, an I/O dedicated cache 14 is provided in front of the memory 2 to which the CPU 11 and the accelerators 12 can commonly access. Data required for data sharing is stored in the I/O dedicated cache 14, whereby data sharing between the CPU 11 and the accelerators 12 can be performed at higher speed and the speed of multimedia processing can be increased.
摘要翻译： [问题]提供一种微处理器，其中当CPU和多个加速器以连接的方式操作时，由于在存储器访问期间的数据共享造成的瓶颈可以被最小化，从而可以实现增强的多媒体处理性能。
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公开(公告)号：US20050172110A1
公开(公告)日：2005-08-04
申请号：US11046453
申请日：2005-01-28
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译： 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。
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公开(公告)号：US06915413B2
公开(公告)日：2005-07-05
申请号：US10101480
申请日：2002-03-20
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
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公开(公告)号：US06839063B2
公开(公告)日：2005-01-04
申请号：US09791817
申请日：2001-02-26
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
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