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公开(公告)号：US5512822A
公开(公告)日：1996-04-30
申请号：US368614
申请日：1995-01-04
申请人： Noboru Masuda
发明人： Noboru Masuda
摘要： A magnetic sensor includes a member having a magnetic contour anisotropy. A counterpart yoke is disposed above a magnet. The thickness of the counterpart yoke is equal to or slightly smaller than the resolution. The counterpart yoke has a magnetic contour anisotropy for restraining the divergence of the magnetic flux from the magnet. The resolution can be prevented from being reduced depending on the distance between a medium and a magnetic sensing element. At the same time, the magnet can be miniaturized.
摘要翻译： 磁传感器包括具有磁轮廓各向异性的构件。 对应的轭架设置在磁体上方。 对应轭的厚度等于或略小于分辨率。 对应的轭具有用于抑制磁通量从磁体发散的磁轮廓各向异性。 可以防止根据介质和磁感测元件之间的距离来减小分辨率。 同时，磁铁可以小型化。
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公开(公告)号：US5430397A
公开(公告)日：1995-07-04
申请号：US186544
申请日：1994-01-26
CPC分类号： G06F1/10 , H03K5/1506
摘要： An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block. The intra-block clock distribution circuitry in each of the blocks responds to the block-destined clock signal supplied to the associated block via one of the block-based clock signal wires connected thereto and the intra-block clock signals fed back via the feedback wires in the associated block to thereby generate a plurality of intra-block clock signals having respective phases which depend on differences in phase between the block-destined clock signal and the fed-back intra-block clock signals.
摘要翻译： 一种LSI内部时钟分配电路，包括主分配电路，多个块内时钟分配电路，与每个块相关联地设置的每个连接到相关块内的多个基于块的时钟信号线中的一个的反馈线 以及相关联的块的块内分布电路，用于将分配到连接到块内时钟信号线的给定一个电路元件的块内时钟信号反馈到该块的块内时钟分配电路。 每个块中的块内时钟分配电路通过经连接到其的基于块的时钟信号线之一和通过反馈线反馈的块内时钟信号来响应提供给相关块的块目的地时钟信号 从而产生具有取决于块目的地时钟信号和反馈块内时钟信号之间的相位差的各个相位的多个块内时钟信号。
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23.发明授权
公开(公告)号：US5278457A
公开(公告)日：1994-01-11
申请号：US901149
申请日：1992-06-19
摘要： The invention relates to method and apparatus for adjusting a clock signal which is supplied to an electronic apparatus. After the turn-on of a power source of the electronic apparatus, it is detected that a temperature of at least a part of devices in the electronic apparatus substantially reaches a saturation state. When the temperature of the device reaches the saturation state, a phase adjustment of the clock signal of the electronic apparatus is executed. After completion of the phase adjustment of the clock signal, its adjusting state is fixed.
摘要翻译： 本发明涉及一种用于调整提供给电子设备的时钟信号的方法和装置。 在电子设备的电源的接通之后，检测到电子设备中的至少一部分设备的温度基本上达到饱和状态。 当器件的温度达到饱和状态时，执行电子设备的时钟信号的相位调整。 在时钟信号的相位调整完成后，其调整状态是固定的。
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公开(公告)号：US4692619A
公开(公告)日：1987-09-08
申请号：US876182
申请日：1986-06-19
申请人： Noboru Masuda , Kenji Tomaki , Tetsuo Oosawa , Michihiro Murata
发明人： Noboru Masuda , Kenji Tomaki , Tetsuo Oosawa , Michihiro Murata
CPC分类号： G01J5/34 , G08B13/191 , Y10S250/01
摘要： A pyroelectric type detecting device including a converging mirror, a pyroelectric type sensor element for detecting light converged by the converging mirror, an amplifier for amplifying an output signal of the sensor element and a casing for accommodating the sensor element and the amplifier. The sensor element has a window for receiving the light and the casing is rotatably mounted on a portion of the converging mirror such that the window of the sensor element confronts a mirror member of the converging mirror.
摘要翻译： 一种热电型检测装置，包括会聚反射镜，用于检测由会聚反射镜会聚的光的热电型传感器元件，用于放大传感器元件的输出信号的放大器和用于容纳传感器元件和放大器的壳体。 传感器元件具有用于接收光的窗口，并且壳体可旋转地安装在会聚反射镜的一部分上，使得传感器元件的窗口面对会聚反射镜的反射镜部件。
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公开(公告)号：US3943481A
公开(公告)日：1976-03-09
申请号：US441630
申请日：1974-02-11
申请人： Noboru Masuda , Yu Nishino , Hisashi Takiguchi
发明人： Noboru Masuda , Yu Nishino , Hisashi Takiguchi
CPC分类号： H01L43/04
摘要： A galvano-magneto effect device in which a glavano-magneto effect element is fixed on a thin substrate and a thick cover plate made of ferrite is provided on said galvano-magneto effect element.
摘要翻译： 在所述电流 - 磁性效应元件上设置有一个电流 - 磁效应器件，其中将一个glavano-磁效应元件固定在一个薄的衬底上，一个由铁氧体制成的厚盖板。
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公开(公告)号：US07944256B2
公开(公告)日：2011-05-17
申请号：US12010597
申请日：2008-01-28
申请人： Noboru Masuda
发明人： Noboru Masuda
IPC分类号： H03L7/06
CPC分类号： H03D13/004 , H03L7/0895 , H03L7/0995 , H03L7/113
摘要： High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely.
摘要翻译： 实现了由PLL电路等表示的各种反馈系统的高精度。 例如，在PLL电路中的电荷泵电路中，在电源电压和输出节点之间设置串联连接的三级PMOS晶体管的第一至第三PMOS晶体管，以及串联连接的第一至第三NMOS晶体管 在地电压和输出节点之间提供三级。 并且，当通过第一脉冲信号在电源电压或接地电压和输出节点之间建立导电性时，第二PMOS晶体管和第二NMOS晶体管被驱动为导通，并且当第一PMOS晶体管和第三NMOS晶体管被驱动为截止时 电导率被第二脉冲信号关闭。 因此，可以通过第一脉冲信号的一个边缘和第二脉冲信号的一个边缘之间的时间差来设置导通时间，因此可以设置短的导通时间，结果是电荷泵电路的充电量 可以精确控制。
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公开(公告)号：US20080218217A1
公开(公告)日：2008-09-11
申请号：US12010597
申请日：2008-01-28
申请人： Noboru Masuda
发明人： Noboru Masuda
CPC分类号： H03D13/004 , H03L7/0895 , H03L7/0995 , H03L7/113
摘要： High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely.
摘要翻译： 实现了由PLL电路等表示的各种反馈系统的高精度。 例如，在PLL电路中的电荷泵电路中，在电源电压和输出节点之间设置串联连接的三级PMOS晶体管的第一至第三PMOS晶体管，以及串联连接的第一至第三NMOS晶体管 在地电压和输出节点之间提供三级。 并且，当通过第一脉冲信号在电源电压或接地电压和输出节点之间建立导电性时，第二PMOS晶体管和第二NMOS晶体管被驱动为导通，并且当第一PMOS晶体管和第三NMOS晶体管被驱动为截止时 电导率被第二脉冲信号关闭。 因此，可以通过第一脉冲信号的一个边缘和第二脉冲信号的一个边缘之间的时间差来设置导通时间，因此可以设置短的导通时间，结果是电荷泵电路的充电量 可以精确控制。
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公开(公告)号：US07105203B1
公开(公告)日：2006-09-12
申请号：US09498749
申请日：2000-02-07
申请人： Noboru Masuda , Masaru Watanabe
发明人： Noboru Masuda , Masaru Watanabe
IPC分类号： B05D5/00
CPC分类号： B05C11/1047 , B05C5/0258 , B05C11/10 , B05D1/26 , B05D5/00 , B05D2252/02
摘要： The intermittent coating apparatus which includes a nozzle 1 which applies a paint 6 to a base material, a feeding side two-way valve 10 which repeats feeding of the paint 6 to the nozzle 1 and stop of the feeding, a return side two-way valve which 11 repeats discharge of the paint 6 to a return side and stop of the discharge, a paint flow path 12, means to feed the paint 6 into the flow path 12, and paint returning means 5 which repeats suction and return of the paint 6 out of and into the nozzle 1, and is characterized in that switching of the feeding side two-way valve 10 is carried out earlier than that of the return side two-way valve 11 within a range not shorter than 5 msec and not longer than 100 msec at least at a coating start time.
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公开(公告)号：US06333645B1
公开(公告)日：2001-12-25
申请号：US09659541
申请日：2000-09-11
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.
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30.发明授权公开(公告)号：US06278296B1
公开(公告)日：2001-08-21
申请号：US09369199
申请日：1999-08-06
申请人： Noboru Masuda , Michitaka Yamamoto
发明人： Noboru Masuda , Michitaka Yamamoto
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced. Therefore, a signal delay time is reduced.
摘要翻译： 在动态逻辑电路中，输入信号的从低到高跃迁与输出信号的低电平到高转换之间的信号延迟时间减小，直流电流减小，预充电所需的时间为 减少 在动态逻辑电路中，P沟道型MOS晶体管（PMOS）的源电极与高压电位Vdd侧的电源连接。 其栅电极接收时钟信号Cs。 逻辑部分包括连接在PMOS的漏电极和低电压电位Vss侧的电源之间的N沟道型MOS晶体管（NMOS）。 在与NMOS中的最接近Vss的NMOS连接的输入信号和Vss之间提供NMOS。 时钟信号Cs的反向信号与NMOS的栅电极连接。 在预充电时强制输入信号变为低电平，从而减小通电流，并减少预充电所需的时间。 因此，信号延迟时间减少。
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