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277 条记录 (耗时 0.057 秒)

    Electrostatic deflector, for electron beam exposure apparatus, with reduced charge-up
    21.
    发明授权
    Electrostatic deflector, for electron beam exposure apparatus, with reduced charge-up 失效
    静电偏转器，用于电子束曝光设备，具有减小的充电

    公开(公告)号：US06268606B1

    公开(公告)日：2001-07-31

    申请号：US09337795

    申请日：1999-06-22

    申请人： Tomohiko Abe ,  Yoshihisa Ooae ,  Hiroshi Yasuda

    发明人： Tomohiko Abe ,  Yoshihisa Ooae ,  Hiroshi Yasuda

    IPC分类号： H01J3700

    CPC分类号： H01J37/1472 ,  H01J2237/1516 ,  H01J2237/3175

    摘要： An electrostatic deflector of an electron beam exposure apparatus is disclosed. A cylindrical holding member is made of an insulating material. An electrode including a plurality of electrode members fixedly arranged in spaced relationship to each other and having at least a portion of the surface thereof grown with a metal film is disposed inside the holding member. The electrode members each formed with a metal film on the surface thereof are made of a conductive ceramic having a resistivity selected at least in the range of 0.001 &OHgr;•cm to 1000 &OHgr;•cm.

    摘要翻译： 公开了电子束曝光设备的静电偏转器。 圆柱形保持构件由绝缘材料制成。 一种电极，其包括以彼此间隔开的关系固定地布置并且其表面的至少一部分由金属膜生长的多个电极部件设置在保持部件的内部。 每个在其表面上由金属膜形成的电极构件由电阻率选择为至少在0.001欧姆·厘米到1000欧姆·厘米的范围内的导电陶瓷制成。

    Method of and system for exposing pattern on object by charged particle beam
    26.
    发明授权
    Method of and system for exposing pattern on object by charged particle beam 失效
    通过带电粒子束对物体曝光图案的方法和系统

    公开(公告)号：US5841145A

    公开(公告)日：1998-11-24

    申请号：US610350

    申请日：1996-03-04

    申请人： Takamasa Satoh ,  Yoshihisa Oae ,  Soichiro Arai ,  Kenichi Miyazawa ,  Hiroshi Yasuda ,  Manabu Ohno ,  Hitoshi Watanabe ,  Junichi Kai ,  Tomohiko Abe ,  Akio Yamada ,  Yasushi Takahashi

    发明人： Takamasa Satoh ,  Yoshihisa Oae ,  Soichiro Arai ,  Kenichi Miyazawa ,  Hiroshi Yasuda ,  Manabu Ohno ,  Hitoshi Watanabe ,  Junichi Kai ,  Tomohiko Abe ,  Akio Yamada ,  Yasushi Takahashi

    IPC分类号： H01J37/302

    CPC分类号： H01J37/3023 ,  H01J2237/3175

    摘要： By using a blanking aperture array BAA, the density of the bit map data in the portions where adjacent areas are linked is decreased toward the outside. On the lower surface of the holder of the BAA chip, a ball grid array wired to blanking electrodes is formed, to be pressed in contact against pads on a wiring base board. The registered bit map data for an isosceles right triangle are read out from address A=A0+�RA.multidot.i! (A0 and i are integers, � ! is an operator for integerizing), masked, and then shifted by bits to be deformed. From registered bit map data for proximity effect correction, the area which corresponds to the size of the object of correction and the required degree of proximity affect correction is extracted, and logic operation with the bit map data of the object of correction is performed to achieve proximity affect correction. Before figures data are expanded into bit map, a checksum is determined in units of bit map data corresponding to the range of one session of scanning over which continuous exposure is possible. A sine wave voltage is provided to an electrostatic deflector and during a one-shot exposure period, an electron beam is caused to scan for an integer number of times on a block of a mask and the positional misalignment of the electron beam at the lower aperture stop is corrected.

    摘要翻译： 通过使用消隐孔径阵列BAA，相邻区域连接的部分中的位图数据的密度朝向外部减小。 在BAA芯片的保持器的下表面上形成布线到消隐电极的球栅阵列，以与接线基板上的焊盘压接。 从地址A = A0 + [RAxi]（A0和i是整数，[]是整数化的运算符）读出等腰直角三角形的注册位图数据，被屏蔽，然后移位以变形。 从用于邻近效应校正的注册位图数据中，提取对应于校正对象的大小的区域和所需的邻近度影响校正程度，并且执行校正对象的位图数据的逻辑运算以实现 近距离影响校正。 在将图形数据扩展为位图之前，以对应于可能进行连续曝光的一次扫描会话的范围的位图数据为单位确定校验和。 向静电偏转器提供正弦波电压，并且在单次曝光期间，使电子束在掩模块上扫描整数次，并且使电子束在下孔处的位置偏移 停止更正。

    Bipolar transistor in bipolar-CMOS technology
    29.
    发明授权
    Bipolar transistor in bipolar-CMOS technology 有权
    双极晶体管在双极CMOS技术

    公开(公告)号：US08536002B2

    公开(公告)日：2013-09-17

    申请号：US13567552

    申请日：2012-08-06

    申请人： Hiroshi Yasuda ,  Berthold Staufer

    发明人： Hiroshi Yasuda ,  Berthold Staufer

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7833

    摘要： A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

    摘要翻译： 通过使用非选择性外延工艺形成双极型晶体管的基极层，使得基极层在集电极有源区域上具有单一结晶区域和多晶硅层，形成包含双极晶体管和MOS晶体管的集成电路的工艺 区域，并且同时注入基极层的MOS栅极层和多晶区域，使得基极 - 集电极结延伸到小于场氧化物深度的三分之一的衬底中，并且垂直累积掺杂 基极层的多晶区域的密度在MOS栅极的垂直累积掺杂密度的80％至125％之间。 包含双极晶体管和通过所描述的工艺形成的MOS晶体管的集成电路。

    Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication
    30.
    发明授权
    Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication 有权
    具有第一双极器件和第二双极器件的半导体器件及其制造方法

    公开(公告)号：US08450179B2

    公开(公告)日：2013-05-28

    申请号：US11670729

    申请日：2007-02-02

    申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

    发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

    摘要： A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.

    摘要翻译： 一种用于制造具有相同掺杂剂类型的第一和第二双极器件的半导体器件的方法包括：在半导体层上沉积介电层，在电介质层上沉积栅极导体层，限定两个双极器件的基极区域， 栅极导体层和电介质层，在栅极导体层和基极区域的暴露的半导体层上沉积基底层，在基底层上沉积绝缘层，形成光致抗蚀剂层并限定两者的发射极区域 去除发射极区域中的光致抗蚀剂层，从而形成两个发射器窗口，掩蔽第一双极器件的发射极窗口，并将第二双极器件的基极区域中的基极层通过相关的发射极窗口暴露于另外的发射体注入 。