Method of making a memory cell having two layered tantalum oxide films
    22.
    发明授权
    Method of making a memory cell having two layered tantalum oxide films 有权
    制造具有两层氧化钽膜的存储单元的方法

    公开(公告)号:US06235572B1

    公开(公告)日:2001-05-22

    申请号:US09334625

    申请日:1999-06-17

    IPC分类号: H01L218242

    摘要: A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode 54 made of a ruthenium film and an upper electrode 62 made of a capacity insulating film 61 and a titanium nitride film and which is connected in series with a memory cell selection MISFET Qs formed on the main surface of a semiconductor substrate 1. The capacity insulating film 61 is made of a multi layered film comprising two layered crystallized tantalum oxide films 56 and 58 each having a film thickness of 10 nm or less. The film thickness of the capacity insulating film 61 is set to 10 to 40 nm.

    摘要翻译: 半导体器件包括具有由信息存储电容器C构成的存储单元的DRAM,该信息存储电容器C包括由钌膜制成的下电极54和由电容绝缘膜61和氮化钛膜制成的上电极62, 与形成在半导体基板1的主表面上的存储单元选择MISFET Qs串联连接。电容绝缘膜61由包括两层结晶的氧化钽膜56和58的多层膜制成,每层具有膜厚度为10 nm以下。 电容绝缘膜61的膜厚设定为10〜40nm。

    Semiconductor device and method of manufacturing the same
    24.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US08278172B2

    公开(公告)日:2012-10-02

    申请号:US12850092

    申请日:2010-08-04

    IPC分类号: H01L21/336 H01L21/28

    摘要: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.

    摘要翻译: 形成半导体器件的方法包括以下处理。 在半导体衬底上形成立柱。 形成覆盖柱的侧面的第一绝缘膜。 去除第一绝缘膜的上部以暴露柱的上部的侧表面。 形成接触插塞,其接触柱的上部的侧表面和柱的顶表面。

    Semiconductor device with capacitor suppressing leak current
    25.
    发明授权
    Semiconductor device with capacitor suppressing leak current 有权
    具有电容器的半导体器件抑制漏电流

    公开(公告)号:US07382014B2

    公开(公告)日:2008-06-03

    申请号:US11434877

    申请日:2006-05-17

    申请人: Shinpei Iijima

    发明人: Shinpei Iijima

    摘要: A semiconductor device with a capacitor includes a lower electrode, a dielectric and an upper electrode on the dielectric layer. The dielectric layer including more than one polycrystalline tantalum oxide layer and more than one separation layer, wherein the polycrystalline tantalum oxide layers and the separation layers are alternately stacked, while one of the polycrystalline tantalum oxide layers is a lowermost layer among the stacked layers.

    摘要翻译: 具有电容器的半导体器件包括在电介质层上的下电极,电介质和上电极。 所述介电层包括多于一个的多晶氧化钽层和多于一个的分离层,其中所述多晶钽氧化物层和所述分离层交替堆叠,而所述多晶钽氧化物层中的一个是所述堆叠层中的最下层。

    Semiconductor device having a stacked capacitor
    26.
    发明申请
    Semiconductor device having a stacked capacitor 审中-公开
    具有层叠电容器的半导体装置

    公开(公告)号:US20060102983A1

    公开(公告)日:2006-05-18

    申请号:US11268558

    申请日:2005-11-08

    申请人: Shinpei Iijima

    发明人: Shinpei Iijima

    IPC分类号: H01L29/00

    摘要: A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4 nm and in contact with the bottom electrode, and an overlying hafnium oxide film having a thickness of 3 to 6 nm. The stacked capacitor has a higher resistance against a biased temperature test.

    摘要翻译: 存储单元中的堆叠电容器具有由金属或金属化合物制成的底部电极,电容器绝缘膜和由金属或金属化合物制成的顶部电极。 电容器绝缘膜包括厚度为2至4nm并与底部电极接触的氧化铝膜和厚度为3至6nm的上覆氧化铪膜。 堆叠式电容器对偏置温度测试具有较高的电阻。

    Process for manufacturing a semiconductor memory device including a memory cell selecting transistor and a capacitor with metal electrodes
    27.
    发明授权
    Process for manufacturing a semiconductor memory device including a memory cell selecting transistor and a capacitor with metal electrodes 有权
    用于制造包括存储单元选择晶体管和具有金属电极的电容器的半导体存储器件的工艺

    公开(公告)号:US06649465B2

    公开(公告)日:2003-11-18

    申请号:US09943506

    申请日:2001-08-31

    IPC分类号: H01L218242

    摘要: A technique is provided which is capable of forming a Ru film constituting a lower electrode of an information storing capacitive element in an aperture with high precision. After a Ru film is deposited, heat treatment is performed in a reducing atmosphere on a side wall and a bottom portion of a deep aperture in which the information storing capacitive element is formed. The deposition and heating of Ru films can be repeated to form a laminated structure of Ru films. As a result, it is possible to effectively remove impurities included in the Ru film, and to achieve fineness of the Ru film.

    摘要翻译: 提供了能够以高精度形成构成孔的信息存储电容元件的下电极的Ru膜的技术。 在沉积Ru膜之后,在形成有信息存储电容元件的深孔的侧壁和底部的还原气氛中进行热处理。 可以重复Ru膜的沉积和加热以形成Ru膜的层压结构。 结果,可以有效地除去Ru膜中所含的杂质,并且实现Ru膜的细度。

    Semiconductor device and method of manufacturing the same
    28.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US08492814B2

    公开(公告)日:2013-07-23

    申请号:US13592865

    申请日:2012-08-23

    IPC分类号: H01L27/06

    摘要: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.

    摘要翻译: 形成半导体器件的方法包括以下处理。 在半导体衬底上形成立柱。 形成覆盖柱的侧面的第一绝缘膜。 去除第一绝缘膜的上部以暴露柱的上部的侧表面。 形成接触插塞,其接触柱的上部的侧表面和柱的顶表面。

    Method of manufacturing a semiconductor device having a stacked capacitor
    29.
    发明授权
    Method of manufacturing a semiconductor device having a stacked capacitor 有权
    制造具有堆叠电容器的半导体器件的方法

    公开(公告)号:US07811895B2

    公开(公告)日:2010-10-12

    申请号:US12464209

    申请日:2009-05-12

    申请人: Shinpei Iijima

    发明人: Shinpei Iijima

    IPC分类号: H01L21/20

    摘要: A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4 nm and in contact with the bottom electrode, and an overlying hafnium oxide film having a thickness of 3 to 6 nm. The stacked capacitor has a higher resistance against a biased temperature test.

    摘要翻译: 存储单元中的堆叠电容器具有由金属或金属化合物制成的底部电极,电容器绝缘膜和由金属或金属化合物制成的顶部电极。 电容器绝缘膜包括厚度为2至4nm并与底部电极接触的氧化铝膜和厚度为3至6nm的上覆氧化铪膜。 堆叠式电容器对偏置温度测试具有较高的电阻。

    Phase-change memory device and method of manufacturing same
    30.
    发明授权
    Phase-change memory device and method of manufacturing same 有权
    相变存储器件及其制造方法

    公开(公告)号:US07498601B2

    公开(公告)日:2009-03-03

    申请号:US11563660

    申请日:2006-11-27

    IPC分类号: H01L29/04

    摘要: A phase-change memory device has a phase-change layer, a heater electrode having an end held in contact with the phase-change layer, a contact plug of different kinds of material having a first electrically conductive material plug made of a first electrically conductive material and held in contact with the other end of the heater electrode, and a second electrically conductive material plug made of a second electrically conductive material having a specific resistance smaller than the first electrically conductive material, the first electrically conductive material plug and the second electrically conductive material plug being stacked in one contact hole, the heater electrode and the second electrically conductive material plug being held in contact with each other in overlapping relation to each other, and an electrically conductive layer electrically connected to the second electrically conductive material plug.

    摘要翻译: 相变存储器件具有相变层,具有与相变层保持接触的端部的加热器电极,具有由第一导电材料制成的第一导电材料塞的不同种类的材料的接触塞 材料并与加热器电极的另一端保持接触;以及第二导电材料塞,其由具有比第一导电材料小的电阻率的第二导电材料制成,第一导电材料塞和第二导电材料塞 导电材料塞被堆叠在一个接触孔中,所述加热器电极和所述第二导电材料塞彼此重叠地保持彼此接触;以及导电层,电连接到所述第二导电材料塞。