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公开(公告)号：US09355730B2
公开(公告)日：2016-05-31
申请号：US14626208
申请日：2015-02-19
IPC分类号： G06F12/00 , G06F12/06 , G11C16/00 , G11C11/56 , G11C16/10 , G06F12/02 , G11C14/00 , G11C16/04 , G11C13/00
CPC分类号： G11C16/107 , G06F12/0246 , G06F12/06 , G06F2206/1014 , G06F2212/7201 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C13/0002 , G11C14/0018 , G11C14/0045 , G11C16/00 , G11C16/0483 , G11C16/10 , G11C2211/5641 , H03M7/14
摘要： The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.
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公开(公告)号：US20160141036A1
公开(公告)日：2016-05-19
申请号：US15007266
申请日：2016-01-27
发明人： Tae-Young KIM
CPC分类号： G11C16/102 , G06F12/0246 , G06F2212/7201 , G11C11/5628 , G11C16/10 , G11C16/107 , G11C16/28 , G11C16/344 , G11C16/3459
摘要： A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells.
摘要翻译： 一种对非易失性存储器件进行重新编程的方法，包括根据连接到位线的页缓冲器的第一和第二锁存器的逻辑值设置所选存储器单元的位线，向所选存储单元提供编程脉冲，执行程序 使用第一和第二锁存器对所选择的存储器单元进行验证操作，并且根据程序验证操作的结果对选择的存储器单元执行预测程序操作。 在预测编程操作中，所选择的存储器单元的位线根据对应于所选择的每个存储器单元的页缓冲器的第三锁存器的逻辑值进行设置。
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公开(公告)号：US09305652B2
公开(公告)日：2016-04-05
申请号：US14191088
申请日：2014-02-26
申请人： SK hynix Inc.
发明人： Hae Soo Kim
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/14 , G11C16/3418
摘要： Provided is a semiconductor memory device and a method of erasing the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit unit configured to apply a pre-erase voltage, an erase voltage, and an erase operation voltage to the memory cell array so as to erase data stored in the plurality of memory cells when an erase operation is performed. The memory cell array includes a plurality of source selection transistors, the plurality of memory cells, and a plurality of drain selection transistors that are connected between a source line and a bit line. When the pre-erase voltage is applied to the source line during the erase operation, different erase operation voltages are applied to an outermost source selection transistor adjacent to the source line among the plurality of source selection transistor and the other selection transistors.
摘要翻译： 提供一种半导体存储器件及其擦除方法。 半导体存储器件包括包括多个存储单元的存储单元阵列; 以及周边电路单元，被配置为向存储单元阵列施加预擦除电压，擦除电压和擦除操作电压，以便当执行擦除操作时擦除存储在多个存储单元中的数据。 存储单元阵列包括多个源极选择晶体管，多个存储单元以及连接在源极线和位线之间的多个漏极选择晶体管。 当在擦除操作期间将预擦除电压施加到源极线时，不同的擦除操作电压被施加到多个源选择晶体管和其它选择晶体管中与源极线相邻的最外面的源极选择晶体管。
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公开(公告)号：US09281068B2
公开(公告)日：2016-03-08
申请号：US14217538
申请日：2014-03-18
发明人： Tae-Young Kim
CPC分类号： G11C16/102 , G06F12/0246 , G06F2212/7201 , G11C11/5628 , G11C16/10 , G11C16/107 , G11C16/28 , G11C16/344 , G11C16/3459
摘要： A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells.
摘要翻译： 一种对非易失性存储器件进行重新编程的方法，包括根据连接到位线的页缓冲器的第一和第二锁存器的逻辑值设置所选存储器单元的位线，向所选存储单元提供编程脉冲，执行程序 使用第一和第二锁存器对所选择的存储器单元进行验证操作，并且根据程序验证操作的结果对选择的存储器单元执行预测程序操作。 在预测编程操作中，所选择的存储器单元的位线根据对应于所选择的每个存储器单元的页缓冲器的第三锁存器的逻辑值进行设置。
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公开(公告)号：US09245590B2
公开(公告)日：2016-01-26
申请号：US14194248
申请日：2014-02-28
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/20 , G11C16/32 , G11C2216/22 , G11C2216/24 , G11C2216/30 , H01L2224/32145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
摘要翻译： 任何数量的串行外围接口（“SPI”）闪存芯片可以使用任何所需的多芯片封装技术进行堆叠和封装，以实现各种功能的任何一种或组合，例如低每位成本，高密度存储，代码阴影 到RAM，以及“执行就绪”应用程序的快速随机访问，同时保留SPI接口的优点。 在器件制造期间，每个堆叠的管芯相对于封装中的另一个堆叠管芯被分配唯一的标识符或“管芯ID”。 在正常操作期间，通过芯片选择指令使用独特的芯片ID，以使堆叠芯片之一能够响应SPI接口上的后续指令，同时禁用软件包中的其他堆叠芯片响应后续指令，但是对于某些“ 通用“指令，包括模切选择指令。 支持堆叠模具的并行操作。
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26.发明申请Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell 审中-公开使用非整数每个单元的位数来管理存储单元中的数据存储公开(公告)号：US20160012883A1
公开(公告)日：2016-01-14
申请号：US14858313
申请日：2015-09-18
申请人： Apple Inc.
发明人： Micha Anholt , Naftali Sommer
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C7/1006 , G11C11/56 , G11C11/5642 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/26 , G11C16/3427
摘要： A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.
摘要翻译： 一种用于数据存储的方法包括：通过使用至少一个外部代码和一个内部代码对数据进行编码，以及在将编码数据存储在存储器单元中之前可选地反转编码数据，将数据存储在一组存储单元中。 从存储器单元读取编码数据，并将内码解码应用于读取的编码数据以产生解码结果。 根据内部代码的解码结果，至少部分读取数据有条件地反转。
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27.发明授权Management of data storage in analog memory cells using a non-integer number of bits per cell 有权使用每个单元的非整数位来管理模拟存储单元中的数据存储公开(公告)号：US09171624B2
公开(公告)日：2015-10-27
申请号：US14135823
申请日：2013-12-20
申请人： Apple Inc.
发明人： Micha Anholt , Naftali Sommer
CPC分类号： G11C11/5628 , G11C7/1006 , G11C11/56 , G11C11/5642 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/26 , G11C16/3427
摘要： A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.
摘要翻译： 一种用于数据存储的方法包括：通过使用至少一个外部代码和一个内部代码对数据进行编码，以及在将编码数据存储在存储器单元中之前可选地反转编码数据，将数据存储在一组存储单元中。 从存储器单元读取编码数据，并将内码解码应用于读取的编码数据以产生解码结果。 根据内部代码的解码结果，至少部分读取数据有条件地反转。
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28.发明授权公开(公告)号：US09159422B1
公开(公告)日：2015-10-13
申请号：US13445139
申请日：2012-04-12
CPC分类号： G11C16/04 , G06F11/1048 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/26
摘要： A method of writing data to non-volatile computer storage is disclosed. A logical page of data is received and stored in an intermediate storage. A first portion of the logical page is read from the intermediate storage and written to a first physical page in the non-volatile computer storage. A second portion of the logical page is read from the intermediate storage and written to a second physical page in the non-volatile computer storage. A method of reading data from non-volatile computer storage is disclosed. A first portion of a logical page is read from a first physical page in the non-volatile computer storage and written in an intermediate storage. A second portion of the logical page is read from a second physical page and written in the intermediate storage. The first portion and the second portion of the logical page are concatenated to form the logical page.
摘要翻译： 公开了向非易失性计算机存储器写入数据的方法。 数据的逻辑页被接收并存储在中间存储器中。 从中间存储器读取逻辑页面的第一部分并写入非易失性计算机存储器中的第一物理页面。 逻辑页面的第二部分从中间存储器读取并写入非易失性计算机存储器中的第二物理页面。 公开了一种从非易失性计算机存储器读取数据的方法。 从非易失性计算机存储器中的第一物理页面读取逻辑页面的第一部分并将其写入中间存储器。 逻辑页面的第二部分从第二物理页面读取并写入中间存储器。 逻辑页面的第一部分和第二部分被级联以形成逻辑页面。
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公开(公告)号：US20150248921A1
公开(公告)日：2015-09-03
申请号：US14194248
申请日：2014-02-28
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/20 , G11C16/32 , G11C2216/22 , G11C2216/24 , G11C2216/30 , H01L2224/32145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
摘要翻译： 任何数量的串行外围接口（“SPI”）闪存芯片可以使用任何所需的多芯片封装技术进行堆叠和封装，以实现各种功能的任何一种或组合，例如低每位成本，高密度存储，代码阴影 到RAM，以及“执行就绪”应用程序的快速随机访问，同时保留SPI接口的优点。 在器件制造期间，每个堆叠的管芯相对于封装中的另一个堆叠管芯被分配唯一的标识符或“管芯ID”。 在正常操作期间，通过芯片选择指令使用独特的芯片ID，以使堆叠芯片之一能够响应SPI接口上的后续指令，同时禁用软件包中的其他堆叠芯片响应后续指令，但是对于某些“ 通用“指令，包括模切选择指令。 支持堆叠模具的并行操作。
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公开(公告)号：US20150243359A1
公开(公告)日：2015-08-27
申请号：US14190265
申请日：2014-02-26
发明人： Rex KHO , Mathew NEAL
CPC分类号： G11C16/107 , G06F21/554 , G11C7/24 , G11C14/009 , G11C16/14 , G11C16/3495
摘要： A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory.
摘要翻译： 一个实施例涉及一种用于处理包括擦除计数器字段的擦除计数器的方法，该方法包括以下步骤：（i）确定未使用的擦除计数器字段; （ii）在未使用的擦除计数器字段中写入选择代码和地址信息，其中组合选择代码和地址信息以确定存储器的至少一个物理地址。
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