公开(公告)号：US20150348623A1

公开(公告)日：2015-12-03

申请号：US14290623

申请日：2014-05-29

Applicant: Intel Corporation

Inventor： Blake Lin ,  Cyrille Dray ,  Ananda Roy ,  Liqiong Wei ,  Faith Hamzaoglu

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0066 ,  G11C2013/0078

Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.

Abstract translation: 描述了用于提高电阻式存储器能量效率和可靠性的装置和方法。 一种装置可以包括耦合到导线的电阻式存储单元。 该装置还可以包括耦合到导线的驱动器，以在写操作期间驱动电阻性存储单元的电流。 在用于检测导线上的电压变化的写入操作期间，可以选择性地增加驱动器的电阻两个或更多个时间段。 当检测到电压变化以提高电阻性存储器的能量效率和可靠性时，用于写入操作的电流可以被关闭。

公开(公告)号：US09183911B2

公开(公告)日：2015-11-10

申请号：US13633479

申请日：2012-10-02

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C2013/0057

Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.

Abstract translation: 一种从自旋转矩磁阻存储器阵列中的多个位读取数据的方法包括执行一个或多个参考的比特的读取操作，以及执行自参考的读取操作，例如破坏性的自参考读取操作， 通过引用的读取操作未成功读取的任何位。 引用的读取操作可以在破坏性自引用读取操作的同一时间或之前启动。

公开(公告)号：US20150243352A1

公开(公告)日：2015-08-27

申请号：US14494806

申请日：2014-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MU-HUI PARK

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/14 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/26 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/71

Abstract: A method of sensing multi-bit data stored in a resistive memory cell includes; determining a resistive value range for the memory cell by performing a first read operation using a first read voltage and a first reference current, determining whether the multi-bit data stored in the resistive memory cell has a first program state, upon determining that the multi-bit data stored does not have the first program state, selecting a second read voltage different from the first read voltage in response to the resistive value range of the resistive memory cell, and using the second read voltage to again determine whether the multi-bit data stored in the resistive memory cell has the first program state.

Abstract translation: 一种感测存储在电阻式存储单元中的多位数据的方法包括： 通过使用第一读取电压和第一参考电流执行第一读取操作来确定存储器单元的电阻值范围，确定存储在电阻性存储单元中的多位数据是否具有第一编程状态， 存储的位数据不具有第一编程状态，响应于电阻性存储单元的电阻值范围选择与第一读取电压不同的第二读取电压，并且使用第二读取电压再次确定多位 存储在电阻性存储单元中的数据具有第一编程状态。

公开(公告)号：US20150194210A1

公开(公告)日：2015-07-09

申请号：US14666360

申请日：2015-03-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shigeki KOBAYASHI ,  Takeshi YAMAGUCHI

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/22 ,  G11C11/00 ,  G11C13/0004 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/71 ,  G11C2213/72

Abstract: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.

Abstract translation: 根据实施例的半导体存储器件包括：控制电路，被配置为将第一电压施加到所选择的第一线，向所选择的第二线施加第二电压，并将第三电压和第四电压施加到未选择的第一线 和设置操作中的未选择的第二行。 控制电路包括检测电路，其被配置为使用参考电压来检测所选存储单元的电阻状态的转变。 控制电路被配置为执行读取操作，其中控制电路将第三电压施加到所选择的第一行和未选择的第一行，将第二电压施加到所选择的第二行，并将第四电压施加到非选择的第二行， - 选择的第二行，并且基于所选择的第二行的电压值设置参考电压。

公开(公告)号：US20140376300A1

公开(公告)日：2014-12-25

申请号：US13924495

申请日：2013-06-21

Applicant: Broadcom Corporation

Inventor： Owen Hynes ,  Jonathan Schmitt

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0057

Abstract: A differential bit cell includes two memory elements that are configured to have different states. Each of the two memory elements is connected to a respective switching element. Each of these switching elements may have process variances, which may result in a degradation of read and/or write margins. To mitigate the effect of such variances, another switching element is coupled to the two memory elements and their respective switching elements in a manner that couples the aforementioned switching elements in a parallel fashion. In this way, the mismatch effects between the switching elements can be negated during read operations. During programming operations, such a configuration allows for the programming of both memory elements to different states with a single current pulse and also reduces the effective resistance of the programming path.

Abstract translation: 差分位单元包括被配置为具有不同状态的两个存储元件。 两个存储元件中的每一个连接到相应的开关元件。 这些开关元件中的每一个可以具有处理方差，这可能导致读取和/或写入边缘的劣化。 为了减轻这种变化的影响，另一个开关元件以以平行的方式耦合上述开关元件的方式耦合到两个存储器元件及其各自的开关元件。 以这种方式，在读取操作期间可以否定开关元件之间的失配效应。 在编程操作期间，这样的配置允许使用单个电流脉冲将两个存储器元件编程到不同状态，并且还减少编程路径的有效电阻。

公开(公告)号：US08913444B1

公开(公告)日：2014-12-16

申请号：US13408797

申请日：2012-02-29

Applicant: Nad Edward Gilbert ,  Ishai Naveh ,  Narbeh Derhacobian

Inventor： Nad Edward Gilbert ,  Ishai Naveh ,  Narbeh Derhacobian

IPC: G11C7/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C11/56 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0011 ,  G11C16/26 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.

Abstract translation: 存储器件和方法可以使用多重检测操作来检测处于边缘状态的存储器元件的状态。 在一些实施例中，评估电路可以响应于相同存储器元件的多个感测结果而产生用于存储器元件的输出值。 在其他实施例中，存储器设备可以包括标准读取操作和强读操作，其中强读操作对于所选择的存储器元件比标准读操作应用更多的能量。

公开(公告)号：US20140321191A1

公开(公告)日：2014-10-30

申请号：US13869512

申请日：2013-04-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/0076

Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.

Abstract translation: 本公开包括用于感测电阻变量存储单元的装置和方法。 多个实施例包括将存储器单元编程为初始数据状态，并通过将编程信号施加到存储器单元，将编程信号与编程存储器单元相关联到特定数据状态来确定存储器单元的数据状态，以及确定是否 在应用编程信号期间，存储单元的数据状态从初始数据状态变为特定数据状态。

公开(公告)号：US20140204663A1

公开(公告)日：2014-07-24

申请号：US13997661

申请日：2011-12-22

Applicant: Robert W. Faber

Inventor： Robert W. Faber

IPC: G11C13/00 ,  G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40618 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/3418 ,  G11C2013/0057 ,  G11C2211/5647

Abstract: An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the PCMS memory device during a refresh of said PCMS memory device.

Abstract translation: 描述了一种装置，其具有反转确定逻辑电路，以确定传输从PCMS存储器件读取的数据的读取数据路径是否被反转或不反转，作为由数据表示的信息是否最后写入反相或非反相 在所述PCMS存储器件的刷新期间，向PCMS存储器件反转逻辑状态。

公开(公告)号：US20140078831A1

公开(公告)日：2014-03-20

申请号：US14029616

申请日：2013-09-17

Applicant: Microchip Technology Incorporated

Inventor： David Francis Mietus

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C7/06 ,  G11C7/062 ,  G11C7/14 ,  G11C16/24 ,  G11C16/28 ,  G11C2013/0057

Abstract: Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage and the “stored” resultant gate-source voltage itself are re-used as the references, or multi-reference, for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.

Abstract translation: 在执行读取之前的位线预充电时间期间可能会使用不存在存储单元的位线出现的电流，以便偏置连接在位线与位线之间的栅极 - 漏极短路PMOS上拉器件 VDD电位的电源。 连接到该PMOS上拉装置的栅极的电容可以用于在预充电时间完成时漏极断开时“存储”所得到的栅极 - 源极电压。 一旦读操作开始，具有“存储的”合成栅源电压和“存储的”合成栅 - 源电压本身的PMOS上拉器件的电流被重新用作参考或多参考， 用于感测在其读取操作期间连接到位线的被断言的存储器单元的状态。

公开(公告)号：US20130322156A1

公开(公告)日：2013-12-05

申请号：US13899092

申请日：2013-05-21

Applicant: International Business Machines Corporation

Inventor： Nikolaos Papandreou ,  Charalampos Pozidis ,  Abu Sebastian

IPC: G11C13/00

CPC classification number: G11C13/0021 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0057

Abstract: A method for read measurement of resistive memory cells having s≧2 programmable cell-states includes applying to each cell at least one initial voltage and making a measurement indicative of cell current due to the initial voltage; determining a read voltage for the cell in dependence on the measurement; applying the read voltage to the cell; making a read measurement indicative of cell current due to the read voltage; and outputting a cell-state metric dependent on the read measurement; wherein the read voltages for cells are determined in such a manner that the cell-state metric exhibits a desired property.