公开(公告)号：US07193534B2

公开(公告)日：2007-03-20

申请号：US11254453

申请日：2005-10-20

Applicant: Hao-Feng Hung

Inventor： Hao-Feng Hung

IPC: H03M1/22

CPC classification number: H03M1/206 ,  H03M1/303

Abstract: The invention provides an interpolation apparatus for improving the resolution of an optical encoder. The optical encoder outputs an encoding signal, and the encoding signal corresponds to a first resolution. The interpolation apparatus comprises a comparing circuit and a lookup table circuit. The comparator receives the encoding signal and produces a plurality of comparison signals. The lookup table circuit receives a plurality of comparison signals and produces an outputted signal, wherein the outputted signal corresponds to second resolution. The second resolution is greater than the first resolution.

Abstract translation: 本发明提供一种用于提高光学编码器分辨率的内插装置。 光学编码器输出编码信号，编码信号对应于第一分辨率。 插值装置包括比较电路和查找表电路。 比较器接收编码信号并产生多个比较信号。 查找表电路接收多个比较信号并产生输出信号，其中输出的信号对应于第二分辨率。 第二项决议大于第一项决议。

公开(公告)号：US20060187105A1

公开(公告)日：2006-08-24

申请号：US11354245

申请日：2006-02-15

Applicant: Kohji Sakata ,  Seiichi Banba ,  Atsushi Wada

Inventor： Kohji Sakata ,  Seiichi Banba ,  Atsushi Wada

IPC: H03M1/12

CPC classification number: H03M1/007 ,  H03M1/002 ,  H03M1/0809 ,  H03M1/167 ,  H03M1/206 ,  H03M1/365

Abstract: An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.

Abstract translation: 具有可变分辨率并且允许降低功耗的模数转换装置。 该装置包括并行类型的模数转换器（ADC），控制器和内插电路。 模数转换器具有并联连接的多个比较器，每个比较器用于比较模拟输入信号和基准信号的电位。 控制器产生用于控制模数转换器的分辨率的控制信号。 具体地，控制器通过控制信号控制比较器（CMP）的数量来操作，从而确定分辨率。 内插电路根据分辨率插值禁用的比较器的输出数据。 当模数转换器以低于其最大分辨率的分辨率操作时，控制器避免同时操作两个相邻的比较器。

公开(公告)号：US06816096B2

公开(公告)日：2004-11-09

申请号：US10421129

申请日：2003-04-23

Applicant: Donald T. Comer ,  Darren S. Korth

Inventor： Donald T. Comer ,  Darren S. Korth

IPC: H03M120

CPC classification number: H03M1/206 ,  H03M1/365

Abstract: An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

公开(公告)号：US5298814A

公开(公告)日：1994-03-29

申请号：US931739

申请日：1992-08-18

Applicant: John Caruso

Inventor： John Caruso

IPC: G06G7/14 ,  H03M1/20 ,  H03M1/36 ,  H03F3/45

CPC classification number: H03M1/206 ,  G06G7/14 ,  H03M1/361

Abstract: An analog voltage averaging circuit using active devices increases speed and resolution in analog to digital converters. The analog to digital converters combine the concepts of residue amplification and averaging to simplify the circuit implementation of high order, high speed analog to digital converters.

Abstract translation: 使用有源器件的模拟电压平均电路可提高模数转换器的速度和分辨率。 模数转换器结合了残差放大和平均的概念，以简化高阶，高速模数转换器的电路实现。

公开(公告)号：US4897657A

公开(公告)日：1990-01-30

申请号：US205854

申请日：1988-06-13

Applicant: James L. Brubaker

Inventor： James L. Brubaker

IPC: H03K19/0948 ,  H03M1/20 ,  H03M1/36 ,  H03M7/16 ,  H03M7/22

CPC classification number: H03M1/206 ,  H03K19/0948 ,  H03M7/165 ,  H03M7/22 ,  H03M1/365

Abstract: Employed is a thermometer-code-to-one-of-n converter having a number of similar portions each of which includes gates each configured to detect a zero-zero-one pattern and to develop a one-of-n signal, gates each configured to detect a one-zero-zero pattern (an invalid pattern) and to develop an error signal, gates configured to combine the error signals, and gates configured to gate the error signals with the one-of-n pattern signals to block (inhibit) one-of-n signals.

Abstract translation: 使用的是具有多个相似部分的温度计 - 一对一转换器，每个转换器包括各自被配置为检测零 - 零模式并且开发一个n信号的门，每个门开 被配置为检测一零零模式（无效模式）并产生误差信号，被配置为组合所述误差信号的门和被配置为将所述误差信号与所述一对n模式信号进行门控的门 禁止）一个n信号。

公开(公告)号：US12052028B2

公开(公告)日：2024-07-30

申请号：US17844413

申请日：2022-06-20

Applicant: SILEAD Inc.

Inventor： Jinling Zhou

IPC: H03M1/12 ,  H03K19/17736 ,  H03K19/20 ,  H03M1/20 ,  H03M1/36 ,  H03M1/46

CPC classification number: H03M1/462 ,  H03K19/1774 ,  H03K19/20 ,  H03M1/206 ,  H03M1/361

Abstract: A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.

公开(公告)号：US08988265B2

公开(公告)日：2015-03-24

申请号：US13941598

申请日：2013-07-15

Applicant: MediaTek Inc.

Inventor： Yun-Shiang Shu

IPC: H03M1/12 ,  H03M1/50 ,  H03M1/20 ,  H03M1/00 ,  H03M1/36

CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

Abstract translation: 提供比较电路并包括第一和第二比较器和第一时间 - 数字比较器。 具有第一偏移电压的第一比较器接收输入信号并产生第一比较信号和第一反比较信号。 第二比较器接收输入信号并产生第二比较信号和第二反比较信号。 第一偏移电压大于第二偏移电压。 第一时间数字比较器接收第一比较信号和第二反比较信号，并根据第一比较信号和第二反比较信号产生第一和第二确定信号。 第一和第二确定信号指示输入信号的电压是否大于第一中间电压。 第一中间电压等于第一偏移电压和第二偏移电压之和的一半。

公开(公告)号：US20110114829A1

公开(公告)日：2011-05-19

申请号：US12618710

申请日：2009-11-14

Applicant: Wei Yan Lee

Inventor： Wei Yan Lee

IPC: G01D5/34

CPC classification number: H03M1/206 ,  H03M1/303

Abstract: Disclosed are various embodiments of front-end analog circuitry for use in conjunction with optical encoders. Highly accurate analog output signals are provided by front-end analog circuitry in incremental or absolute motion encoders to interpolation circuitry, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.

Abstract translation: 公开了与光学编码器一起使用的前端模拟电路的各种实施例。 高精度模拟输出信号由增量式或绝对运动编码器的前端模拟电路提供给插值电路，能够提供具有高定时精度的高内插因子输出信号。 公开的内插电路可以使用CMOS或BiCMOS处理而不用过度的努力来实现。

公开(公告)号：US20100007541A1

公开(公告)日：2010-01-14

申请号：US12439444

申请日：2007-08-10

Applicant: Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

Inventor： Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

IPC: H03M1/34

CPC classification number: H03M1/0624 ,  H03M1/206 ,  H03M1/365

Abstract: The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

Abstract translation: 传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

公开(公告)号：US07450049B2

公开(公告)日：2008-11-11

申请号：US11803392

申请日：2007-05-14

Applicant: Shigenori Yamauchi ,  Takamoto Watanabe

Inventor： Shigenori Yamauchi ,  Takamoto Watanabe

IPC: H03M1/60

CPC classification number: H03M1/206 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

Abstract: The digitization apparatus includes, as a main scale, a pulse delay circuit constituted by a plurality of delay units connected in series or in ring form, a latch/encoder, a circulation number counter, and a latch circuit, and includes, as a vernier, a reverse timing extraction circuit detecting a reverse timing at which any one of the delay units has reversed, and an interpolation circuit. The main scale digitizes a time interval between two successive measurement signals in a resolution equal to a delay time per one delay unit. The vernier digitizes a time difference between a measurement timing indicated by the measurement signal and the reverse timing in a resolution equal to 1/M (M being an integer not smaller than 2). The interpolation circuit includes two delay lines each constituted by a plurality of delay units connected in series or in ring form.

Abstract translation: 数字化装置包括作为主要尺度的由串联或环形连接的多个延迟单元，锁存/编码器，循环号计数器和锁存电路构成的脉冲延迟电路，并且包括作为游标 检测任一个延迟单元已经反转的反向定时的反向定时提取电路和内插电路。 主比例数字化两个连续的测量信号之间的时间间隔，其分辨率等于每个延迟单元的延迟时间。 游标数字化测量信号所示的测量定时与反向定时之间的时差，其分辨率等于1 / M（M为不小于2的整数）。 插补电路包括两个延迟线，每条延迟线由串联或环形连接的多个延迟单元构成。