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公开(公告)号：US11671288B2
公开(公告)日：2023-06-06
申请号：US17517042
申请日：2021-11-02
申请人： Kandou Labs, S.A.
发明人： Ali Hormati , Richard Simpson
CPC分类号： H04L25/03949 , H04L7/0087 , H04L7/033 , H04L25/03057 , H04L25/03885 , H04L7/0025
摘要： Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
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公开(公告)号：US20230156149A1
公开(公告)日：2023-05-18
申请号：US18093802
申请日：2023-01-05
发明人： Yalcin Balcioglu
IPC分类号： H04N7/12 , G06F1/04 , H03M3/00 , H04L7/033 , H04N21/234 , H04N21/2365 , H04N21/414 , H04N7/10
CPC分类号： H04N7/12 , G06F1/04 , H03M3/428 , H04L7/033 , H04N21/234 , H04N21/2365 , H04N21/41422 , H04N7/108 , H04N7/104 , G09G2310/08 , H03L7/193
摘要： Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.
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公开(公告)号：US20230155808A1
公开(公告)日：2023-05-18
申请号：US18155809
申请日：2023-01-18
发明人： Kenji NAKAGAWA , Koji TOMITSUKA
摘要： A transmission device included in one base station in a radio communication system including communication areas adjacent to each other in which the base station communicates with a plurality of wireless terminals includes: a modulation unit that generates a data symbol sequence; a synchronization signal generating unit that generates a first symbol sequence constituted by two or more continuous repetitions of reference sequence symbols being a reference, generates a second symbol sequence by performing frequency shifting on the first symbol sequence by using a phase rotation sequence so that the reference sequence symbols become orthogonal for each of the wireless terminals, and generates a synchronization signal; and a synchronization signal adding unit that generates a transmission signal by adding the synchronization signal to the data symbol sequence.
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24.发明申请公开(公告)号：US20190245677A1
公开(公告)日：2019-08-08
申请号：US16268485
申请日：2019-02-05
发明人： Jing Yang Chen , Robert S. Nemiroff
CPC分类号： H04L7/033 , H04L43/106
摘要： A system and method are provided for encoding and decoding multiplexed video signals to de-jitter the content. A first de-jitter operation is performed on incoming signals and a second de-jitter operation is performed on PCR modified outbound packetized signals after sequencing of the packetized signals has been determined. In one case the second de-jitter operation can be performed using a PLL that is based, at least in part, on the output hardware limitations.
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公开(公告)号：US20190199507A1
公开(公告)日：2019-06-27
申请号：US16293412
申请日：2019-03-05
申请人： FINISAR CORPORATION
发明人： Jason Y. MIAO
CPC分类号： H04L7/0079 , H03L7/087 , H04L5/1438 , H04L7/033 , H04L25/03057
摘要： A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.
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公开(公告)号：US20190173661A1
公开(公告)日：2019-06-06
申请号：US16156868
申请日：2018-10-10
申请人： Rambus Inc.
发明人： Marko Aleksic , Simon Li , Roxanne Vu
CPC分类号： H04L7/033 , H03L7/081 , H04L7/0004 , H04L7/0079 , H04L7/0337 , H04L25/0292 , H04L25/03 , H04L25/03057 , H04L2025/03802
摘要： A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
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公开(公告)号：US20180278195A1
公开(公告)日：2018-09-27
申请号：US15858485
申请日：2017-12-29
发明人： Tobias Bernhard Fritz , Martin Staebler , Baher Haroun , Peter Fundaro , Jiri Panacek , Ralf Peter Brederlow
CPC分类号： H02P27/085 , H02M3/157 , H03M9/00 , H04L7/033 , H04L7/06 , H04Q11/02 , H04Q11/04 , H04Q11/06 , H04Q2213/036 , H04Q2213/13036
摘要： A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.
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公开(公告)号：US10084623B1
公开(公告)日：2018-09-25
申请号：US14946397
申请日：2015-11-19
CPC分类号： H04L7/0033 , H04L7/0004 , H04L7/0079 , H04L7/033 , H04L25/03019 , H04L27/01
摘要： Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.
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公开(公告)号：US10063365B1
公开(公告)日：2018-08-28
申请号：US15455485
申请日：2017-03-10
申请人： Keyssa Systems, Inc.
发明人： Jerome Jean Ribo , Bruno Tourette
CPC分类号： H04L7/005 , H03L7/07 , H03L7/0807 , H03L7/0812 , H04L7/0037 , H04L7/033 , H04L25/242
摘要： Methods, systems, and apparatus for inserting a re-timer signal between a transmitter and a receiver, including receiving, from the transmitter, an input data signal having encoded words, where each encoded word of the encoded words has a word length of a predetermined number of bits; generating, by a re-timer and based on the input data signal, a regenerated clock signal and an output data signal; determining, based on the regenerated clock signal, a timing difference between the input data signal and the output data signal of the re-timer; and applying, by the re-timer and based on the timing difference between the input data signal and the output data signal, a delay to the input data signal to generate a delayed output data signal, such that a timing difference between the input data signal and the delayed output data signal corresponds to N word lengths.
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公开(公告)号：US10057050B2
公开(公告)日：2018-08-21
申请号：US15399815
申请日：2017-01-06
申请人： FUJITSU LIMITED
发明人： Yukito Tsunoda
CPC分类号： H04L7/0331 , H03L7/0805 , H03L7/0807 , H03L7/087 , H03L7/099 , H04L7/0004 , H04L7/033
摘要： A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal.
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