公开(公告)号：US5369047A

公开(公告)日：1994-11-29

申请号：US87645

申请日：1993-07-01

申请人： Jaroslav Hynecek

发明人： Jaroslav Hynecek

IPC分类号： H01L27/148 ,  H01L21/72

CPC分类号： H01L27/148

摘要： The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.

摘要翻译： 图像传感器电荷检测放大器具有电荷存储阱60，用于感测电荷存储阱60中的电荷水平的电荷传感器32，与电荷存储阱60相邻的电荷泄漏28，以及用于从电荷转移电荷的电荷转移结构 存储阱60连接到电荷漏极28。

公开(公告)号：US5332686A

公开(公告)日：1994-07-26

申请号：US129454

申请日：1993-09-29

申请人： William E. Glenn

发明人： William E. Glenn

IPC分类号： G06F11/10 ,  G11C5/00 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L21/72

CPC分类号： H01L29/7881 ,  G06F11/1008 ,  G06F11/1076 ,  G11C16/04 ,  H01L27/115 ,  Y10S438/907

摘要： Method for producing a large capacity solid-state memory wherein thin film technology is used to form a plurality of large-area arrays of memory cells, each of which is fabricated in a continuous process on a thin flexible substrate to form an elongate tape. The plurality of tapes are assembled into a compact package by winding them, one upon the other, into a spool which is placed in a suitable housing.

摘要翻译： 用于制造大容量固态存储器的方法，其中使用薄膜技术来形成多个大面积存储单元阵列，每个存储单元阵列以连续的方式制造在薄柔性基板上以形成细长带。 多个带通过将它们彼此缠绕而组装成紧凑的包装件，并将其放置在放置在合适的外壳中的线轴中。

公开(公告)号：US5324682A

公开(公告)日：1994-06-28

申请号：US55074

申请日：1993-04-29

申请人： Hua Q. Tserng

发明人： Hua Q. Tserng

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L21/72

CPC分类号： H01L27/0605 ,  H01L21/8252

摘要： In one form of the invention, an integrated circuit for providing low-noise and high-power microwave operation is disclosed comprising: a) a material structure formed during a single epitaxial growth cycle, said structure comprising: i) a substrate 10; ii) a donor layer 16 above the substrate; iii) a first wide bandgap buffer layer 18 above the donor layer; iv) an undoped first channel layer 19 above the first wide bandgap layer; v) a second channel layer 24 above the first channel layer; and vi) a second wide bandgap layer 26 above the second channel layer; b) a first device 80 fabricated of the material structure comprising: i) a first source contact 50 to said first channel layer; ii) a first drain contact 54 to said first channel layer; and iii) a first gate contact 38 above the first channel layer; and c) a second device 82 fabricated of the material structure comprising: i) a second source contact 52 to said second channel layer; ii) a second drain contact 56 to said second channel layer; and iii) a second gate 46 contacting the second wide band-gap layer.

摘要翻译： 在本发明的一种形式中，公开了一种用于提供低噪声和高功率微波操作的集成电路，其包括：a）在单个外延生长周期期间形成的材料结构，所述结构包括：i）衬底10; ii）衬底上方的施主层16; iii）施主层上方的第一宽带隙缓冲层18; iv）在第一宽带隙层上方的未掺杂的第一沟道层19; v）在第一沟道层上方的第二沟道层24; 和vi）在第二通道层上方的第二宽带隙层26; b）由材料结构制造的第一装置80，包括：i）到所述第一沟道层的第一源极接触50; ii）到所述第一通道层的第一漏极接触54; 和iii）在第一通道层上方的第一栅极触点38; 以及c）由所述材料结构制造的第二装置82，包括：i）到所述第二沟道层的第二源极接触52; ii）到所述第二通道层的第二漏极接触56; 和iii）与第二宽带隙层接触的第二栅极46。

公开(公告)号：US5296402A

公开(公告)日：1994-03-22

申请号：US88188

申请日：1993-07-06

申请人： Eui K. Ryou

发明人： Eui K. Ryou

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/72

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/1082 ,  H01L28/40

摘要： A semiconductor memory device and a method for manufacturing the same, capable of increasing the effective cell capacitor area by virtue of steps each defined between a semiconductor substrate surface and each field oxide film formed over the semiconductor substrate. Over the semiconductor substrate, a thin film MOSFET is formed, which includes a charge storage electrode and an active region both connected with a charge storage electrode of each memory cell through a charge storage contact hole. With this structure, a second effective capacitor area is obtained, thereby enabling the capacitance to increase. Also, the semiconductor substrate is connected with a substrate of the thin film MOSFET by a substrate contact hole. Accordingly, it is possible to control the electrical characteristic of the thin film MOSFET. In spite of a decrease in cell area, a higher charge storage capacity can be also obtained.

摘要翻译： 一种半导体存储器件及其制造方法，其能够通过在半导体衬底表面和半导体衬底上形成的每个场氧化物膜之间的步骤来增加有效单元电容器面积。 在半导体衬底上形成薄膜MOSFET，其包括电荷存储电极和有源区，两者均通过电荷存储接触孔与每个存储单元的电荷存储电极相连。 利用该结构，获得第二有效电容器面积，从而使电容增加。 此外，半导体衬底通过衬底接触孔与薄膜MOSFET的衬底连接。 因此，可以控制薄膜MOSFET的电特性。 尽管电池面积减小，但也可获得更高的电荷存储容量。

公开(公告)号：US4074139A

公开(公告)日：1978-02-14

申请号：US754685

申请日：1976-12-27

申请人： Jacques I. Pankove

发明人： Jacques I. Pankove

IPC分类号： H01J37/317 ,  H01J49/28 ,  H01J37/30 ,  H01L21/265 ,  H01L21/72

CPC分类号： H01J49/286 ,  H01J37/3172

摘要： A method and apparatus for implanting dopant material into a substrate of semiconductive material in a preselected pattern without utilizing a mask comprises the use of a source template which is formed of the desired dopant material in the configuration of the pattern to be implanted. Ions of the dopant material are sputtered from the template by bombardment with an ionized gas, and these dopant ions are then filtered from unwanted ion species and accelerated into the substrate while remaining in the original template pattern.

摘要翻译： 在不利用掩模的情况下，以预选图案将掺杂剂材料注入到半导体材料的衬底中的方法和装置包括在待植入图案的配置中使用由所需掺杂剂材料形成的源模板。 掺杂剂材料的离子通过用电离气体轰击从模板溅射，然后将这些掺杂剂离子从不需要的离子物质中过滤并加速到衬底中，同时保留在原始模板图案中。

公开(公告)号：US5401681A

公开(公告)日：1995-03-28

申请号：US277916

申请日：1994-07-20

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/72

CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90

摘要： A method of forming a bit line over capacitor array of memory cells includes, a) providing an array of word lines; b) providing active areas about the word lines to define an array of memory cell FETs; c) providing a layer of electrically insulating material over the word lines and active areas; d) providing first and second respective contact openings through the insulating material layer to capacitor and bit contact active regions; e) providing electrically conductive material within the first and second contact openings which electrically connects with the respective capacitor and bit active regions, with the electrically conductive material within the respective first and second contact openings collectively extending elevationally over and above the insulating material upper surface, the electrically conductive material within the first contact openings electrically connecting with the electrically conductive material of the second contact openings above the insulating material upper surface; and f) in a single step, chemical-mechanical polishing the collective electrically conductive material extending over and above the insulating material upper surface downwardly to at least the upper surface of the insulating material, the single chemical-mechanical polishing step effectively electrically isolating the conductive material within the first contact openings from the conductive material within the second contact openings.

摘要翻译： 在存储器单元的电容器阵列上形成位线的方法包括：a）提供字线阵列; b）提供关于字线的有源区域以定义存储单元FET阵列; c）在字线和有效区域上提供一层电绝缘材料; d）提供通过绝缘材料层到电容器和钻头接触有效区域的第一和第二相应接触开口; e）在第一和第二接触开口内提供导电材料，其与相应的电容器和位有源区域电连接，相应的第一和第二接触开口内的导电材料共同地在绝缘材料上表面上方和上方延伸， 所述第一接触开口内的所述导电材料与所述绝缘材料上表面上方的所述第二接触开口的导电材料电连接; 和f）在单一步骤中，化学机械抛光在绝缘材料上表面上方和上方延伸至至少绝缘材料的上表面的集体导电材料，单个化学机械抛光步骤有效地电绝缘导电 在第一接触开口内的第二接触开口内的导电材料的材料。

公开(公告)号：US5387535A

公开(公告)日：1995-02-07

申请号：US196060

申请日：1994-02-14

申请人： Klaus Wilmsmeyer

发明人： Klaus Wilmsmeyer

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/72

CPC分类号： H01L21/76889 ,  H01L21/76895

摘要： A method of fabricating CMOS devices with local interconnects is disclosed which is performed in two stages. In the first stage, a SALICIDE process is carried out, and in the second stage, the local interconnects are formed.

摘要翻译： 公开了一种制造具有局部互连的CMOS器件的方法，其分两个阶段执行。 在第一阶段，进行SALICIDE处理，在第二阶段形成局部互连。

公开(公告)号：US5293336A

公开(公告)日：1994-03-08

申请号：US784519

申请日：1991-10-29

申请人： Takeaki Ishii ,  Satoshi Maeda

发明人： Takeaki Ishii ,  Satoshi Maeda

IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/72

CPC分类号： H01L27/1085 ,  H01L21/8234 ,  H01L27/10805 ,  H01L27/105

摘要： A semiconductor memory device has a memory cell composed of a select MOS transistor and information storage capacitor and a peripheral circuit composed of a MOS transistor formed at a peripheral side of the memory cell, these transistors being formed in the surface portion of a first conductivity type semiconductor substrate. In the semiconductor memory device, the gate oxide film of the select MOS transistor is different in thickness from the gate oxide film of the MOS transistor of the peripheral circuit, the gate electrodes of these transistors being simultaneously formed.

摘要翻译： 半导体存储器件具有由选择MOS晶体管和信息存储电容器构成的存储单元，以及由形成在存储单元周边的MOS晶体管构成的外围电路，这些晶体管形成在第一导电型的表面部分 半导体衬底。 在半导体存储器件中，选择MOS晶体管的栅极氧化膜的厚度与外围电路的MOS晶体管的栅极氧化膜的厚度不同，这些晶体管的栅电极同时形成。

公开(公告)号：US5262344A

公开(公告)日：1993-11-16

申请号：US661707

申请日：1991-02-26

申请人： Kaizad R. Mistry

发明人： Kaizad R. Mistry

IPC分类号： H01L27/02 ,  H01L29/45 ,  H01L21/336 ,  H01L21/72

CPC分类号： H01L29/456 ,  H01L27/0266

摘要： An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.

摘要翻译： ESD保护器件由N沟道接地栅晶体管形成在集成电路中。 该保护装置具有多晶硅栅极，就像集成电路器件中的其它P-沟道晶体管和N沟道晶体管一样，但是保护器件的硅化物被控制，使ESD事件的不利影响最小化。 在保护器件的多晶硅栅极之上不产生硅化物区域，也不在栅极附近的源极/漏极区域上与栅极自对准，因为由CMOS工艺制造的其它晶体管。 通过使用沉积的氧化物层作为掩模来防止栅极附近的保护晶体管的硅化，并且该氧化物层也用于形成用于晶体管栅极的侧壁间隔物。 侧壁间隔物用于在除了保护晶体管之外的所有P-沟道晶体管和N沟道晶体管的栅/漏区之上产生自对准硅化物区域。 可以使用制造具有自对准硅化物源极/漏极区域的CMOS集成电路的标准工艺，仅添加一个非关键掩模步骤来阻挡保护晶体管的硅化。

公开(公告)号：US4822755A

公开(公告)日：1989-04-18

申请号：US185600

申请日：1988-04-25

申请人： William G. Hawkins ,  Donald J. Drake ,  Michael R. Campanelli

发明人： William G. Hawkins ,  Donald J. Drake ,  Michael R. Campanelli

IPC分类号： H01L21/302 ,  B41J2/16 ,  H01L21/301 ,  H01L21/306 ,  H01L29/06 ,  H01L21/00 ,  H01L21/02 ,  H01L21/72 ,  H01L21/98

CPC分类号： B41J2/1628 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1629 ,  B41J2/1642 ,  H01L21/30604 ,  B41J2202/13 ,  H01L29/0657 ,  Y10S438/928

摘要： A method for separating chips formed on a silicon substrate is provided which uses a combination of reactive ion etching techniques combined with orientation etching to yield integrated chips having edges which can be more precisely butted together to form large area arrays.