公开(公告)号：US20240097672A1

公开(公告)日：2024-03-21

申请号：US17949454

申请日：2022-09-21

申请人： Apple Inc.

发明人： Yueming He ,  Dennis M. Fischette, JR.

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K17/167 ,  H03K19/00361

摘要： An integrated circuit may be provided with power switching circuitry. The power switching circuitry may include a primary power switch and multiple auxiliary power switches. A power gating control circuit may output control signals for selectively activating the primary power switch and at least one of the auxiliary power switches to charge a gated voltage. One or more voltage detectors may be configured to monitor the gated voltage and to activate the remaining auxiliary power switches in response to detecting that the gated voltage exceeds one or more thresholds. Configured and operated in this way, inrush current surge protection can be achieved while charging up the gated voltage sufficiently fast.

公开(公告)号：US11936372B2

公开(公告)日：2024-03-19

申请号：US18188144

申请日：2023-03-22

申请人： Magnachip Semiconductor, Ltd.

发明人： Jung Hoon Sul ,  Dong Il Seo

IPC分类号： H03K17/16 ,  H03F3/45 ,  H03K5/04

CPC分类号： H03K17/161 ,  H03F3/45179 ,  H03K5/04 ,  H03F2200/552 ,  H03F2203/45248

摘要： A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

公开(公告)号：US11916543B2

公开(公告)日：2024-02-27

申请号：US17897845

申请日：2022-08-29

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Shigeo Imai

IPC分类号： H03K17/06 ,  H03K17/16

CPC分类号： H03K17/063 ,  H03K17/162 ,  H03K2217/0018

摘要： An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT

公开(公告)号：US20240063785A1

公开(公告)日：2024-02-22

申请号：US18466601

申请日：2023-09-13

申请人： pSemi Corporation

发明人： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC分类号： H03K17/10 ,  H01L25/065 ,  H01L27/07 ,  H01L27/12 ,  H03K17/0412 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693

CPC分类号： H03K17/102 ,  H01L25/0657 ,  H01L27/0727 ,  H01L27/1203 ,  H03K17/0412 ,  H03K17/063 ,  H03K17/162 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/6874 ,  H03K17/693 ,  H03K2017/066 ,  H03K2217/0009 ,  H03K2217/0054

摘要： A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US11909383B2

公开(公告)日：2024-02-20

申请号：US17624085

申请日：2020-06-18

申请人： Thomas Meier

发明人： Thomas Meier

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K17/06 ,  H04B3/06

CPC分类号： H03K17/162 ,  H03K17/063 ,  H03K17/687 ,  H04B3/06 ,  H03K2217/0054

摘要： The invention relates to an electrical circuit (1) for transmitting a useful analogue signal, which has a signal transmission path (16) with an input path (2) and an output path (3) and at least one switch (6), with which the useful signal which is carried on the input path (2) can be connected through to the output path (3) or the signal transmission path (16) can be interrupted. According to the invention, a compensation circuit (4) which substantially compensates for a distortion of the useful analogue useful signal generated by the at least one switch (6) when it is switched off (OFF) is provided, wherein the compensation circuit (4) is connected to a control terminal (G) of the at least one switch (6) and comprises at least one non-linear capacitance.

公开(公告)号：US11901459B2

公开(公告)日：2024-02-13

申请号：US17549839

申请日：2021-12-13

申请人： pSemi Corporation

发明人： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Robert B. Welstand ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae-Youn Kim

IPC分类号： G06F7/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H03K17/16

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

摘要： A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

公开(公告)号：US20240048136A1

公开(公告)日：2024-02-08

申请号：US18207986

申请日：2023-06-09

申请人： National University Corporation Tokai National Higher Education and Research System ,  TOYODA GOSEI CO., LTD.

发明人： Toshihiro IWAKI ,  Daisuke Arai ,  Masayoshi Yamamoto ,  Toshiya Uemura ,  Hisao Sato ,  Masao Kamiya

IPC分类号： H03K17/081 ,  H03K17/16 ,  H03K19/0185

CPC分类号： H03K17/08104 ,  H03K17/162 ,  H03K19/018521

摘要： A semiconductor device includes a first transistor including a normally-on transistor with a first source, a first drain, and a first gate and a second transistor including a normally-off transistor with a second source, a second drain electrically connected to the first source, and a second gate. A first gate signal, which turns on later than a second gate signal at the time of turn-on of the device and turns off earlier than the second gate signal at the time of turn-off of the device, is input to the first gate. The second gate signal, which turns on earlier than the first gate signal at the time of the turn-on and turns off later than the first gate signal at the time of the turn-off, is input to the second gate. An amount of delay of each of the first gate signal and the second gate signal is set independently.

公开(公告)号：US20240039526A1

公开(公告)日：2024-02-01

申请号：US17875876

申请日：2022-07-28

申请人： Infineon Technologies AG

发明人： Guang ZENG ,  Franz-Josef NIEDERNOSTHEIDE ,  Mark-Matthias BAKRAN ,  Zheming LI

IPC分类号： H03K17/16

CPC分类号： H03K17/166 ,  H03K17/168 ,  H03K2217/0027

摘要： A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

公开(公告)号：US20240030923A1

公开(公告)日：2024-01-25

申请号：US18478572

申请日：2023-09-29

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： John Laurence PENNOCK ,  John Paul LESSO

IPC分类号： H03K19/0948 ,  H03K17/16 ,  H03K19/003 ,  H03M1/00

CPC分类号： H03K19/0948 ,  H03K17/161 ,  H03K19/00346 ,  H03K19/00369 ,  H03M1/001

摘要： This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

公开(公告)号：US20240022161A1

公开(公告)日：2024-01-18

申请号：US17865482

申请日：2022-07-15

申请人： GM GLOBAL TECHNOLOGY OPERATIONS LLC

发明人： Hong Nguyen ,  Michael Z. Pieszala ,  Yilun Luo ,  Khorshed Mohammed Alam ,  Sanjeev M. Naik ,  Benjamin S. Ngu

IPC分类号： H02M1/08 ,  H02M7/5395 ,  H03K17/16

CPC分类号： H02M1/08 ,  H02M7/5395 ,  H03K17/16

摘要： A variable current gate driver for a transistor includes a first current control device having a first controllable output current. The first current control device is electrically connected between a first bus and an activator of the transistor, and a second current control device having a second controllable output current. The second current control device is electrically connected between the activator of the transistor and a second bus. A controller is operatively connected to the first and second current control devices to control the first and second controllable output currents to control the first and second current control devices to control activation of the transistor via the activator. The controller is operative to control the first and second current control devices to control a slew rate of the transistor.