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    SYSTEM AND METHOD FOR MINIMIZING FLOATING GATE TO FLOATING GATE COUPLING EFFECTS DURING PROGRAMMING IN FLASH MEMORY
    293.
    发明申请
    SYSTEM AND METHOD FOR MINIMIZING FLOATING GATE TO FLOATING GATE COUPLING EFFECTS DURING PROGRAMMING IN FLASH MEMORY 审中-公开

    公开(公告)号：US20200176060A1

    公开(公告)日：2020-06-04

    申请号：US16783286

    申请日：2020-02-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： VIPIN TIWARI ,  NHAN DO ,  HIEU VAN TRAN

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

    Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

    Programming Methods For Neural Network Using Non-volatile Memory Array
    294.
    发明申请
    Programming Methods For Neural Network Using Non-volatile Memory Array 审中-公开

    公开(公告)号：US20200151543A1

    公开(公告)日：2020-05-14

    申请号：US16746852

    申请日：2020-01-18

    Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

    Inventor： Farnood Merrikh BAYAT ,  Xinjie GUO ,  Dmitri STRUKOV ,  Nhan DO ,  Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN

    IPC: G06N3/04 ,  G06F3/06 ,  G06N3/063

    Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

    Method Of Making Split Gate Non-volatile Flash Memory Cell
    298.
    发明申请
    Method Of Making Split Gate Non-volatile Flash Memory Cell 审中-公开

    公开(公告)号：US20200020789A1

    公开(公告)日：2020-01-16

    申请号：US16576370

    申请日：2019-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

    Address Fault Detection In A Flash Memory System
    299.
    发明申请
    Address Fault Detection In A Flash Memory System 审中-公开

    公开(公告)号：US20190378548A1

    公开(公告)日：2019-12-12

    申请号：US16551593

    申请日：2019-08-26

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Xian Liu ,  Nhan Do

    IPC: G11C7/10 ,  H01L21/28 ,  H01L27/11521 ,  G11C8/12

    Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

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