公开(公告)号：US20150249179A1

公开(公告)日：2015-09-03

申请号：US14627038

申请日：2015-02-20

Applicant: STMicroelectronics SA

Inventor： Bruno Rauber

IPC: H01L31/112 ,  H01L31/02 ,  H01L31/028

CPC classification number: H01L27/1446 ,  H01L31/101 ,  H01L31/11

Abstract: A photodetector is formed in a silicon-on-insulator (SOI) type semiconductor layer. The photodetector includes a first region and a second region of a first conductivity type separated from each other by a central region of a second conductivity type so as to define a phototransistor. A transverse surface of the semiconductor layer is configured to receive an illumination. The transverse surface extends orthogonally to an upper surface of the central region.

Abstract translation: 在绝缘体上硅（SOI）型半导体层中形成光检测器。 光电检测器包括第一导电类型的第一区域和第二区域，第二区域通过第二导电类型的中心区域彼此分开，以便限定光电晶体管。 半导体层的横向表面被配置为接收照明。 横向表面垂直于中心区域的上表面延伸。

公开(公告)号：US09092590B2

公开(公告)日：2015-07-28

申请号：US14105382

申请日：2013-12-13

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Philippe Flatresse ,  Matthieu Le Boulaire ,  Jean-Philippe Noel

IPC: G06F17/50 ,  H01L21/84

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/84

Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

Abstract translation: 包括排列成一排的第一和第二FDSOI UTBOX单元的IC，其中第一和第二FDSOI UTBOX单元排列成一行，其中第一和第二FOSOI UTBOX单元布置成具有和接地平面以上的nMOS晶体管和N型阱，以及配置有接地平面以上的铅垂和P 型井，N型阱和P型阱布置在行轴的任一侧，其中第二个包括防止天线效应的二极管或阱分接电池，第二电池包括P型阱 被布置成pMOS晶体管的P型阱的对准并且包括以nMOS晶体管的N型阱的排列方式布置的N型阱，第二单元包括耦合到其P型阱的金属连接 并且连接到具有N型井的高级金属连接元件排列的铅垂，金属连接在轴的任一侧延伸。

公开(公告)号：US09083324B2

公开(公告)日：2015-07-14

申请号：US14024508

申请日：2013-09-11

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Andreia Cathelin ,  Janusz Grzyb ,  Yan Zhao

IPC: H03K3/03 ,  H03L7/099 ,  H03B27/00 ,  H03L7/23

CPC classification number: H03K3/0315 ,  H03B27/00 ,  H03L7/099 ,  H03L7/23

Abstract: A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator.

Abstract translation: 频率振荡器包括具有串联耦合的N个反相器的环形振荡器，其中N是等于3或更大的奇整数。 第一滤波器耦合在第一反相器的输出节点和频率振荡器的输出线之间。 第二滤波器耦合在第二反相器的输出节点和频率振荡器的输出线之间。

公开(公告)号：US20150145768A1

公开(公告)日：2015-05-28

申请号：US14553216

申请日：2014-11-25

Applicant: STMicroelectronics SA

Inventor： Marc Drader ,  Jérémie Teyssier ,  Olivier Pothier

IPC: G06F3/01 ,  G01B11/14 ,  G06F3/03 ,  G01C9/06

CPC classification number: G06F3/017 ,  G01B11/14 ,  G01C9/06 ,  G01C2009/066 ,  G01S17/08 ,  G01S17/875 ,  G06F3/0325 ,  G06F3/0421

Abstract: A method for controlling an apparatus, includes steps of: determining distance measurements of an object in a first direction, using distance sensors defining between them a second direction different from the first direction, assessing a first inclination of the object in relation to a second direction based on the distance measurements, and determining a first command of the apparatus according to the inclination assessment.

Abstract translation: 一种用于控制装置的方法，包括以下步骤：使用在它们之间限定与第一方向不同的第二方向的距离传感器来确定物体在第一方向上的距离测量，评估物体相对于第二方向的第一倾斜度 基于距离测量，以及根据倾斜评估确定装置的第一命令。

公开(公告)号：US09029955B2

公开(公告)日：2015-05-12

申请号：US13933396

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L29/786 ,  H01L27/12 ,  H01L29/732 ,  H01L29/06

CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

公开(公告)号：US20150116029A1

公开(公告)日：2015-04-30

申请号：US14523996

申请日：2014-10-27

Applicant: STMicroelectronics SA

Inventor： Antoine Litty ,  Sylvie Ortolland

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/1087 ,  H01L29/78624 ,  H01L29/78648 ,  H03K17/687

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract translation: 延伸漏极晶体管形成在绝缘层的一侧上的半导体层中，半导体区域布置在绝缘层的另一侧上。 半导体区域包括布置在源极的前面的第一导电类型的第一部分和栅极的至少一个较大部分和布置在延伸漏极区域的至少较大部分的前面的第二导电类型的第二部分 所述第一和第二部分中的每一个耦合到连接垫。

公开(公告)号：US09018729B2

公开(公告)日：2015-04-28

申请号：US13895715

申请日：2013-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Raul Andres Bianchi ,  Pascal Fonteneau

IPC: H01L23/58 ,  H01L31/0256 ,  H01L27/144 ,  H01L31/18 ,  H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC classification number: H01L31/0256 ,  H01L27/144 ,  H01L29/0684 ,  H01L29/66113 ,  H01L29/866 ,  H01L31/1892

Abstract: An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.

Abstract translation: 一种平均二极管，包括布置在半导体区域的表面处的相反导电类型的两个重掺杂区域之间的轻掺杂区域，重掺杂区域之间的轻掺杂区域的长度L大约在50和 200nm。

公开(公告)号：US09000840B2

公开(公告)日：2015-04-07

申请号：US14134167

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Yvain Thonnart ,  Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel

IPC: H01L25/00 ,  H03K3/012 ,  G05F3/02 ,  H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L27/118 ,  H01L29/786

CPC classification number: H03K3/012 ,  G05F3/02 ,  G06F1/10 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648

Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.

Abstract translation: 与包括第一和第二相对掺杂的半导体阱的块集成。 存在彼此相邻放置的标准单元，每个标准单元包括第一晶体管和由标准单元包围的时钟树单元。 时钟树单元具有与第一阱和第二晶体管的掺杂相同的掺杂类型的第三半导体阱。 时钟树单元还具有围绕第三阱连续延伸的半导体条，并且具有与第三阱的掺杂相反的掺杂类型，以将第三阱与第一阱电隔离。

公开(公告)号：US20150091116A1

公开(公告)日：2015-04-02

申请号：US14503460

申请日：2014-10-01

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Patrick Gros D'aillon ,  Michel Marty

IPC: H01L27/146 ,  G02B5/20

CPC classification number: H01L27/14621 ,  G02B5/20 ,  G02B5/281 ,  G02B5/286 ,  G02B5/288 ,  H01L27/14685 ,  H04N9/045

Abstract: A stack of layers defines a filter and is formed by copper on hydrogenated silicon nitride supported by a carrier. The filter includes a layer of hydrogenated silicon nitride, a layer of silicon oxide on the layer of hydrogenated silicon nitride and a layer of copper on the layer of silicon oxide. The layer of hydrogenated silicon nitride may have, in a vicinity of its upper side, a ratio of a number of silicon atoms per cubic centimeter to a number of nitrogen atoms per cubic centimeter lower than 0.8 (or even lower than 0.6), with a number of silicon-hydrogen bonds smaller than or equal to 6×1021 bonds per cubic centimeter (or even smaller than 0.5×1021 bonds per cubic centimeter). The filter further includes an additional layer of copper between the layer of hydrogenated silicon nitride and the carrier.

Abstract translation: 一叠层限定了过滤器，并由由载体支撑的氢化氮化硅上的铜形成。 滤波器包括氢化氮化硅层，氢化氮化硅层上的氧化硅层和氧化硅层上的铜层。 氢化氮化硅层可以在其上侧附近具有每立方厘米的硅原子数与每立方厘米低于0.8（或甚至低于0.6）的氮原子数的比率，其中a 硅 - 氢键的数量小于或等于每立方厘米6×1021键（或甚至小于每立方厘米0.5×1021的键）。 滤波器还包括在氢化氮化硅层和载体之间的附加的铜层。

公开(公告)号：US20150091106A1

公开(公告)日：2015-04-02

申请号：US14498091

申请日：2014-09-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： SÉBASTIEN BARNOLA ,  YVES MORAND ,  HEIMANU NIEBOJEWSKI

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract translation: 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。