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291.发明申请公开(公告)号：US20180100774A1
公开(公告)日：2018-04-12
申请号：US15289360
申请日：2016-10-10
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Nitin Bansal
CPC classification number: G01K15/005 , G01K1/14 , G01K7/01 , H01L23/34 , H01L23/345 , H01L29/73
Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor a varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
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公开(公告)号：US09929728B2
公开(公告)日：2018-03-27
申请号：US15185514
申请日：2016-06-17
Applicant: STMicroelectronics International N.V.
Inventor： Ankit Agrawal
IPC: H03K17/10 , H01L29/786 , H01L29/06 , H01L29/78 , H01L27/12 , H01L29/10 , H01L27/092 , H03K17/687 , H01L29/423
CPC classification number: H03K17/102 , H01L27/092 , H01L27/1203 , H01L29/0653 , H01L29/1033 , H01L29/42364 , H01L29/7838 , H01L29/78648 , H03K17/6872
Abstract: A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.
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公开(公告)号：US09928458B2
公开(公告)日：2018-03-27
申请号：US15397559
申请日：2017-01-03
Applicant: STMicroelectronics International N.V.
Inventor： Vinko Kunc , Anton Stern , Kosta Kovacic , Albin Pevec , Maksimiljan Stiglic
IPC: G06K19/06 , G06K19/077 , G06K19/07
CPC classification number: G06K19/07773 , G06K19/0715 , G06K19/07749 , G06K19/0775
Abstract: An RFID transponder device has antenna terminals for coupling an antenna system to the device. A transmitter and a receiver are coupled to the antenna terminals. The device has at least one damping resistance connected to at least one of the antenna terminals. The at least one damping resistance is connected, depending on a voltage swing at the antenna terminals during a transmission burst period, either together with a serially connected switch in parallel to the antenna terminals that are coupled to the receiver, or together with a parallel connected switch between one of the antenna terminals and a terminal of the transmitter. A damping control is configured to activate the at least one damping resistance during a damping period after the transmission burst period by controlling the respective switch.
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294.发明申请公开(公告)号：US20180083602A1
公开(公告)日：2018-03-22
申请号：US15460520
申请日：2017-03-16
Inventor： Alok Kumar Tripathi , Amit Verma , Pascal Urard
CPC classification number: H03K3/356104 , H03K3/012 , H03K3/35625 , H03K19/0002
Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.
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公开(公告)号：US20180069552A1
公开(公告)日：2018-03-08
申请号：US15257693
申请日：2016-09-06
Applicant: STMicroelectronics International N.V.
Inventor： Prashant Singh
IPC: H03K19/0185 , H03K3/356 , H03K19/00
CPC classification number: H03K19/018521 , H03K3/356104 , H03K19/0013
Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.
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Patent Agency Ranking
公开(公告)号：US09898030B2
公开(公告)日：2018-02-20
申请号：US15207732
申请日：2016-07-12
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri
Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.
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公开(公告)号：US20180020338A1
公开(公告)日：2018-01-18
申请号：US15472907
申请日：2017-03-29
Applicant: STMicroelectronics International N.V.
Inventor： Nicolas Cordier , Vinko Kunc , Maksimiljan Stiglic
CPC classification number: H04W8/005 , H04B5/0025 , H04W4/80 , H04W48/10
Abstract: According to an embodiment, a method can be performed by a first active near-field communication (NFC) device. The method includes assuming a field detection mode, generating an advertisement pulse, and checking whether a predefined condition is fulfilled. If the checking determines that the predefined condition is fulfilled, the method includes assuming an active mode and communicating with an adjacent active NFC device, and, if the checking does not determine that the predefined condition is fulfilled, the method includes staying in the field detection mode and generating another advertisement pulse.
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公开(公告)号：US20180017986A1
公开(公告)日：2018-01-18
申请号：US15207732
申请日：2016-07-12
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri
Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.
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公开(公告)号：US20180013389A1
公开(公告)日：2018-01-11
申请号：US15713145
申请日：2017-09-22
Applicant: STMicroelectronics International N.V.
Inventor： Vinod KUMAR
IPC: H03F1/02 , H03K17/687 , H01L29/786 , H01L21/84 , H01L29/94 , G05F3/16 , H01L29/78 , H01L29/66 , H03L7/093 , H03F3/193
CPC classification number: H03F1/0205 , G05F3/16 , H01L21/84 , H01L29/66181 , H01L29/7831 , H01L29/78603 , H01L29/78648 , H01L29/94 , H03F3/193 , H03F2200/451 , H03K17/687 , H03L7/093
Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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公开(公告)号：US20180011141A1
公开(公告)日：2018-01-11
申请号：US15203362
申请日：2016-07-06
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/31723 , G01R31/31727 , G01R31/31855 , G01R31/318552
Abstract: A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).
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