公开(公告)号：US20020080965A1

公开(公告)日：2002-06-27

申请号：US09995258

申请日：2001-11-27

Applicant: STMicroelectronics S.A.

Inventor： Fabrice Marinet ,  Alexandre Malherbe

IPC: H04L009/00

CPC classification number: G06F7/588 ,  G06K19/073 ,  G06K19/07363 ,  H03K3/84

Abstract: A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.

Abstract translation: 随机信号发生器使用其漏源电流包括随机分量的折叠MOS晶体管作为电子噪声源。 随机信号发生器从随机分量生成随机二进制信号。 本发明特别可以应用于智能卡。

公开(公告)号：US20020079949A1

公开(公告)日：2002-06-27

申请号：US10085845

申请日：2002-02-26

Applicant: STMicroelectronics S.A.

Inventor： Christophe Moreaux

IPC: H01H037/76

CPC classification number: H01L27/118 ,  H03K19/1731 ,  H03K19/1736

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

公开(公告)号：US20020079589A1

公开(公告)日：2002-06-27

申请号：US10046322

申请日：2001-10-23

Applicant: STMicroelectronics S.A.

Inventor： Philippe Gayet ,  Eric Granger

IPC: H01L021/4763 ,  H01L023/02

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers. Further, at least one electrical connection element is provided in the third dielectric layer and passes through the second dielectric layer until it comes into contact with the first dielectric layer.

Abstract translation: 一种用于制造集成电路的方法。 根据该方法，在第一电介质层的上方形成第二电介质层，并且在第一和第二电介质层中蚀刻空穴和/或沟槽。 孔和/或沟槽用金属填充以形成电连接元件，并且形成至少第三介电层。 为了控制蚀刻的深度，孔和/或沟槽相对于第一介电层和元件在第三介电层和第二介质层中被选择性蚀刻。 此外，提供了一种具有由电介质层分离的金属化水平和连接不同金属化水平线的金属化通孔的类型的集成电路。 集成电路包括第一和第二金属化层，位于第一金属化层上方的第一和第二叠置电介质层，以及位于第一和第二电介质层上方的第三电介质层。 此外，至少一个电连接元件设置在第三电介质层中并且通过第二电介质层，直到其与第一电介质层接触。

公开(公告)号：US20020043989A1

公开(公告)日：2002-04-18

申请号：US09972233

申请日：2001-10-05

Applicant: STMicroelectronics S.A.

Inventor： Jean-Francois Hugues ,  Pascal Vivet

IPC: H03K019/00

CPC classification number: G06F11/1695 ,  G06F9/3871 ,  G06F11/167

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

公开(公告)号：US20020021116A1

公开(公告)日：2002-02-21

申请号：US09864869

申请日：2001-05-24

Applicant: STMicroelectronics S.A.

Inventor： Philippe Sirito-Olivier

IPC: G05F003/16

CPC classification number: G05F3/265 ,  Y10S323/907

Abstract: A current source with low temperature dependence includes a reference current source and a current mirror for copying the reference source current to at least one output branch. The reference current source and the current mirror may have opposite coefficients of temperature dependence and the current mirror may be a weighted mirror. The present invention is particularly applicable to the manufacture of integrated circuits.

Abstract translation: 具有低温度依赖性的电流源包括参考电流源和用于将参考源电流复制到至少一个输出分支的电流镜。 参考电流源和电流镜可以具有相反的温度依赖系数，并且电流镜可以是加权镜。 本发明特别适用于集成电路的制造。

公开(公告)号：US20020019083A1

公开(公告)日：2002-02-14

申请号：US09915753

申请日：2001-07-26

Applicant: STMicroelectronics S.A.

Inventor： Herve Jaouen ,  Vincent Le Goascoz

IPC: H01L021/84 ,  H01L021/00 ,  H01L021/331 ,  H01L021/8222

CPC classification number: H01L21/76264 ,  H01L21/76275 ,  H01L21/76278

Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.

Abstract translation: 从具有两个平行主表面的第一半导体衬底制造包括由绝缘材料包围并放置在另一绝缘材料上的半导体材料的胰岛的系统的方法包括形成第一绝缘材料层，并在 第一半导体衬底的顶部主表面是形成半导体材料的小岛的薄的半导体层。 可以相对于第一半导体衬底选择性地蚀刻薄半导体层。 在半导体材料的胰岛和薄半导体层的暴露表面上形成第二绝缘材料层。 该方法还包括移除第一半导体衬底。

公开(公告)号：US20020014676A1

公开(公告)日：2002-02-07

申请号：US09898540

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Helene Baudry ,  Francois Leverd

IPC: H01L029/00

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/763

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract translation: 在制造晶体管之前，在衬底中形成深绝缘沟槽的相位之后是在衬底中形成浅绝缘沟槽并延伸深沟槽的相位。 形成深沟槽的相位包括用初始氧化层涂覆深沟槽的内壁，并且在由绝缘材料形成的封套内的硅填充深沟槽。 形成浅沟槽的相位包括用初始氧化层涂覆浅沟槽的内壁，并用绝缘材料填充浅沟槽。

公开(公告)号：US20010053569A1

公开(公告)日：2001-12-20

申请号：US09812717

申请日：2001-03-20

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Michel Haond

IPC: H01L021/335

CPC classification number: H01L29/66772 ,  H01L29/78648

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

Abstract translation: 制造MOS晶体管的方法包括在绝缘体上硅衬底内形成第一栅极，形成横向覆盖第一栅极的半导体沟道区，以及在沟道区的每一侧上形成半导体漏极和源极区。 半导体沟道区域和漏极和源极区域可以通过在第一栅极的上表面上外延生长。 通道区域可以通过在通道区域下形成隧道并且用第一电介质至少部分地填充隧道而与第一栅极的上表面隔离。 第二栅极形成在沟道区域上并且横向于沟道区域。 第二栅极可以通过第二电介质与沟道区的上表面分离。

公开(公告)号：US20010051413A1

公开(公告)日：2001-12-13

申请号：US09796116

申请日：2001-02-28

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Michel Marty ,  Helene Baudry

IPC: H01L021/331

CPC classification number: H01L29/66242

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract translation: 该方法包括在半导体衬底的基极区域上依次形成多晶Ge或多晶硅层，在Ge或SiGe层的选定区域上的蚀刻停止层，相同的多晶硅层 导电类型作为基极区，然后是外层介电材料。 蚀刻层包括在停止层处停止以形成发射器窗预制件，去除停止膜并选择性地去除发射器窗预制件中的Ge或SiGe层以形成发射极窗并形成由导电性的多晶硅制成的发射极 键入窗口中的基础区域的相反。

公开(公告)号：US20010050387A1

公开(公告)日：2001-12-13

申请号：US09814177

申请日：2001-03-21

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Didier Dutartre ,  Pascal Ribot ,  Maryse Paoli ,  Richard Fournel

IPC: H01L029/76

CPC classification number: H01L29/66825 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42336

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract translation: 非易失性存储器包括在源极和漏极区域之间的衬底中延伸的浮动栅极。 通道区域可以被两个绝缘层限制。 本发明特别适用于使用CMOS技术的EPROM，EEPROM，闪存和单电子存储器。