公开(公告)号：US10468428B1

公开(公告)日：2019-11-05

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US10431265B2

公开(公告)日：2019-10-01

申请号：US15467174

申请日：2017-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Xian Liu ,  Nhan Do

IPC: G11C16/06 ,  G11C7/10 ,  G11C8/12 ,  H01L21/28 ,  H01L27/11521 ,  G11C16/08 ,  G11C29/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04 ,  G11C8/08 ,  G11C8/10 ,  G11C29/12 ,  H01L27/11524

Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. An address fault detection array is used to confirm that an activated word line or bit line is the word line or bit line that was actually intended to be activated based upon the received address, which will identify a type of fault where the wrong word line or bit line is activated. The address fault detection array also is used to indicate whether more than one word line or bit line was activated, which will identify a type of fault where two or more word lines or bit lines are activated.

公开(公告)号：US20190287631A1

公开(公告)日：2019-09-19

申请号：US15990220

申请日：2018-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G06N3/08

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US10418451B1

公开(公告)日：2019-09-17

申请号：US16057750

申请日：2018-08-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Chien-Sheng Su ,  Jeng-Wei Yang

IPC: H01L29/788 ,  H01L21/321 ,  H01L29/423 ,  H01L23/532 ,  H01L29/08 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/324 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3215 ,  H01L21/265

Abstract: A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.

公开(公告)号：US10388389B2

公开(公告)日：2019-08-20

申请号：US16271673

申请日：2019-02-08

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11558 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04 ,  H01L29/788 ,  H01L27/11524

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20190244669A1

公开(公告)日：2019-08-08

申请号：US16387377

申请日：2019-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US20190198647A1

公开(公告)日：2019-06-27

申请号：US16287581

申请日：2019-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02 ,  H01L27/11536

CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11536 ,  H01L28/00 ,  H01L29/423 ,  H01L29/42328

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10312247B1

公开(公告)日：2019-06-04

申请号：US15933124

申请日：2018-03-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11524 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

Abstract: A non-volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.

公开(公告)号：US10311958B2

公开(公告)日：2019-06-04

申请号：US15593231

申请日：2017-05-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US20190121556A1

公开(公告)日：2019-04-25

申请号：US16228313

申请日：2018-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/04 ,  H01L21/78 ,  H01L23/00 ,  H01L29/423 ,  G11C16/10 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.