公开(公告)号：US20140223269A1

公开(公告)日：2014-08-07

申请号：US14175955

申请日：2014-02-07

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/10

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

公开(公告)号：US20140149775A1

公开(公告)日：2014-05-29

申请号：US14232187

申请日：2012-06-20

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3293 ,  G06F13/1694 ,  Y02D10/151 ,  Y02D10/157

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract translation: 动态地改变设备之间的信息传输的带宽以适应系统中使用的功率模式之间的转换。 通过选择性地启用和禁用携带信息的各个控制链路和数据链路来改变带宽。 在系统的最高带宽模式下，所有的数据和控制链路都可以在整个过程中提供最大的信息。 在系统的一个或多个较低带宽模式期间，禁用至少一个数据链路和/或至少一个控制链路以减少设备的功耗。 在每个低带宽模式期间，至少一个数据链路和至少一个控制链路保持使能。 对于这些链路，相同的信令速率用于两种带宽模式，以减少由信号速率变化引起的延迟。 此外，为禁用的链接生成校准信息，以便这些链接可以快速恢复使用。

公开(公告)号：US20140098622A1

公开(公告)日：2014-04-10

申请号：US14104188

申请日：2013-12-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory controller outputs a clock signal to first and second DRAMs disposed on a memory module, the clock signal requiring respective first and second time intervals to propagate to the first and second DRAMs. The memory controller outputs a write command to be sampled by the first and second DRAMs at times indicated by the first clock signal and outputs, in association with the write command, first and second write data to the first and second DRAMs, respectively. The memory controller further outputs first and second strobe signals respectively to the first and second DRAMs, the first strobe signal to time reception of the first and second write data therein. The memory controller adjusts respective transmission times of the first and second strobe signals to be offset from one another by a time interval that corresponds to a difference between the first and second time intervals.

Abstract translation: 存储器控制器将时钟信号输出到设置在存储器模块上的第一和第二DRAM，所述时钟信号需要相应的第一和第二时间间隔来传播到第一和第二DRAM。 存储器控制器在由第一时钟信号指示的时间输出由第一和第二DRAM采样的写入命令，并且与写入命令相关联地分别将第一和第二写入数据输出到第一和第二DRAM。 存储器控制器还分别向第一和第二DRAM输出第一和第二选通信号，第一选通信号在其中时间接收第一和第二写入数据。 存储器控制器将第一和第二选通信号的相应传输时间调整为相应于第一和第二时间间隔之间的差的时间间隔彼此偏移。

公开(公告)号：US08693556B2

公开(公告)日：2014-04-08

申请号：US13846413

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L25/00

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：US08665662B2

公开(公告)日：2014-03-04

申请号：US13712842

申请日：2012-12-12

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract translation: 根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

公开(公告)号：US20130176763A1

公开(公告)日：2013-07-11

申请号：US13728330

申请日：2012-12-27

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path.

Abstract translation: 公开了一种堆叠式存储器，其包括具有第一存储位置并与第二集成电路存储器芯片堆叠的第一集成电路存储器芯片。 冗余存储器由第一和第二集成电路存储器芯片共享，并且具有选择性地替换第一或第二集成电路存储器芯片中的相应存储位置的冗余存储位置。 堆叠式存储器还包括用于耦合到外部集成电路存储器控制器和相应的第一和第二信号路径的引脚接口。 第一信号路径通过第一和第二集成电路存储器芯片形成，并且耦合到冗余存储器和引脚接口。 第二信号路径通过第一和第二集成电路存储器芯片形成，并且经由第一信号路径耦合到冗余存储器和引脚接口。

公开(公告)号：US12253903B2

公开(公告)日：2025-03-18

申请号：US18140133

申请日：2023-04-27

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F13/42 ,  H03M13/00 ,  H03M13/09 ,  H03M13/29 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1867

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

公开(公告)号：US12236111B2

公开(公告)日：2025-02-25

申请号：US18610888

申请日：2024-03-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

公开(公告)号：US20250021484A1

公开(公告)日：2025-01-16

申请号：US18782890

申请日：2024-07-24

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/0864

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US20250021450A1

公开(公告)日：2025-01-16

申请号：US18782440

申请日：2024-07-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G06F3/06 ,  G11C7/20 ,  G11C14/00

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.