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    TAG-BASED IMPLEMENTATIONS ENABLING HIGH SPEED DATA CAPTURE AND TRANSPARENT PRE-FETCH FROM A NOR FLASH
    312.
    发明申请
    TAG-BASED IMPLEMENTATIONS ENABLING HIGH SPEED DATA CAPTURE AND TRANSPARENT PRE-FETCH FROM A NOR FLASH 有权
    基于标签的实现，从NOR闪存启用高速数据捕获和透明预备

    公开(公告)号：US20150318049A1

    公开(公告)日：2015-11-05

    申请号：US14266010

    申请日：2014-04-30

    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Ankur Behl ,  Gregory Poivre

    IPC: G11C16/32 ,  G11C7/22 ,  G06F9/44 ,  G11C7/10

    CPC classification number: G06F9/44 ,  G06F1/08 ,  G06F1/10 ,  G06F9/4401 ,  G06F9/4403 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/0416 ,  G11C16/32

    Abstract: Embodiments disclosed herein generally relate for efficiently retrieving boot code for a processor from serial NOR flash memory. When a boot code request is received, a request handler in data capture logic tags successive address read requests to indicate whether the requests indicate contiguous addresses in the NOR flash memory for the boot code. Different circuitry in the data capture logic operates on different mesochronous clock signals. One clock signal drives the capture of boot code from NOR flash, and the other controls synchronized tagging, storing, pre-fetching, and transmitting of the captured boot code data.

    Abstract translation: 本文公开的实施例通常涉及从串行NOR闪速存储器有效地检索处理器的引导代码。 当接收到引导代码请求时，数据捕获逻辑中的请求处理器标记连续的地址读取请求，以指示请求是否指示用于引导代码的NOR闪存中的连续地址。 数据采集​​逻辑中的不同电路在不同的同步时钟信号上运行。 一个时钟信号驱动从NOR闪存捕获引导代码，另一个控制器同步标记，存储，预取和发送捕获的引导代码数据。

    Low power reference generator circuit
    314.
    发明授权
    Low power reference generator circuit 有权
    低功率参考发生器电路

    公开(公告)号：US09170595B2

    公开(公告)日：2015-10-27

    申请号：US13650829

    申请日：2012-10-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: H02M3/02 ,  G05F3/24

    CPC classification number: G05F3/24 ,  G05F3/245

    Abstract: A PTAT circuit includes a first, second, third, and fourth transistors plus a resistor. The first and second transistors have control terminals coupled to each other. The third and fourth transistors have control terminals coupled to each other. The third transistor sources a first current to the first transistor and the fourth transistor sources a second current to the second transistor. The resistor is coupled at a node to the second transistor. A current source circuit sources additional current into the node that is derived from the first and second currents. In one implementation, the additional current is a scaled mirror of the second current. In another implementation, the additional current is a scaled mirror of the sum of the first and second currents. An output current is obtained by mirroring one of the first-third currents. A band-gap output voltage is obtained by applying the additional current across a resistance.

    Abstract translation: PTAT电路包括第一，第二，第三和第四晶体管加上电阻器。 第一和第二晶体管具有彼此耦合的控制端子。 第三和第四晶体管具有彼此耦合的控制端子。 第三晶体管向第一晶体管馈送第一电流，而第四晶体管将第二电流馈送至第二晶体管。 电阻器在一个节点处耦合到第二晶体管。 电流源电路将来自第一和第二电流的额外电流输入到节点中。 在一个实现中，附加电流是第二电流的缩放镜。 在另一实施方案中，附加电流是第一和第二电流之和的经比例的镜。 通过镜像第一至第三电流之一获得输出电流。 通过在电阻上施加附加电流来获得带隙输出电压。

    Low drop-out regulator with a current control circuit
    315.
    发明授权
    Low drop-out regulator with a current control circuit 有权
    具有电流控制电路的低压差稳压器

    公开(公告)号：US09170591B2

    公开(公告)日：2015-10-27

    申请号：US14018967

    申请日：2013-09-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Alexandre Pons

    IPC: G05F1/571 ,  G05F1/56

    CPC classification number: G05F1/56 ,  G05F1/575

    Abstract: A circuit including a low drop-out regulator (LDO) has a current control loop configured and connected to detect whether an external capacitor is connected to the output of the LDO. The current control loop includes a differential amplifier, a current source capable to output different reference currents and a small MOS transistor. The circuit may be operated in an output capacitor detection mode when started and in a regulated voltage source mode otherwise. In the output capacitor detection mode, the small MOS transistor is driven by the differential amplifier and drives the LDO's power MOS transistor depending on a difference between a current through the small MOS transistor and the reference current output by the current source. Components of the current control loop may be used during regulated voltage source mode for short circuit protection.

    Abstract translation: 包括低压差稳压器（LDO）的电路具有配置和连接的电流控制回路，以检测外部电容器是否连接到LDO的输出端。 电流控制回路包括差分放大器，能够输出不同参考电流的电流源和小型MOS晶体管。 电路可以在启动时以输出电容器检测模式工作，否则在稳压电源模式下工作。 在输出电容检测模式下，小型MOS晶体管由差分放大器驱动，并根据通过小MOS晶体管的电流与电流源输出的参考电流之间的差异驱动LDO的功率MOS晶体管。 电流控制回路的组件可在调节电压源模式下用于短路保护。

    Method of Computing State of Charge and Battery State of Charge Monitor
    317.
    发明申请
    Method of Computing State of Charge and Battery State of Charge Monitor 审中-公开
    计费充电状态和充电状态的方法

    公开(公告)号：US20150276885A1

    公开(公告)日：2015-10-01

    申请号：US14225192

    申请日：2014-03-25

    Applicant: STMicroelectronics International N.V.

    Inventor： Hariharasudhan K.R. ,  Ramkumar S.

    IPC: G01R31/36

    CPC classification number: H02J7/0047 ,  G01R31/367 ,  G01R31/3842 ,  H02J2007/005

    Abstract: Disclosed herein are a method of computing an estimated SOC and a battery state of charge (SOC) monitor. An embodiment method for computing an estimated SOC includes periodically measuring a present battery current and a present battery voltage. A hysteresis compensation value is then computed based on a previous SOC, the present battery current, and the present battery voltage when a change in battery current exceeds a threshold. The estimated SOC is then determined based on the hysteresis compensation value and a baseline SOC determined based on the present battery voltage and the present battery current.

    Abstract translation: 这里公开了一种计算估计的SOC和电池充电状态（SOC）监视器的方法。 用于计算估计SOC的实施例方法包括周期性地测量当前电池电流和当前电池电压。 然后，当电池电流的变化超过阈值时，基于先前的SOC，当前的电池电流和当前的电池电压来计算滞后补偿值。 然后基于滞后补偿值和基于当前电池电压和当前电池电流确定的基线SOC来确定估计的SOC。

    Programmable delay introducing circuit in self timed memory
    318.
    发明授权
    Programmable delay introducing circuit in self timed memory 有权
    自定时存储器中的可编程延迟引入电路

    公开(公告)号：US09147453B2

    公开(公告)日：2015-09-29

    申请号：US14532174

    申请日：2014-11-04

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

    IPC: H05B1/02 ,  G11C7/22 ,  G11C7/06 ,  G11C7/08 ,  G11C29/12 ,  G11C29/14 ,  G11C29/50

    CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

    Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。

    INTEGRATED CIRCUIT CAPACITORS FOR ANALOG MICROCIRCUITS
    319.
    发明申请
    INTEGRATED CIRCUIT CAPACITORS FOR ANALOG MICROCIRCUITS 有权
    用于模拟微处理器的集成电路电容器

    公开(公告)号：US20150270393A1

    公开(公告)日：2015-09-24

    申请号：US14219786

    申请日：2014-03-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Vinod Kumar

    IPC: H01L29/78 ,  H01L29/94 ,  H01L29/66 ,  H03K17/687 ,  H01L29/06 ,  H03L7/08 ,  G05F3/16 ,  H01L29/36 ,  H01L21/84

    CPC classification number: H03F1/0205 ,  G05F3/16 ,  H01L21/84 ,  H01L29/66181 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/94 ,  H03F3/193 ,  H03F2200/451 ,  H03K17/687 ,  H03L7/093

    Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

    Abstract translation: 双栅极FD-SOI晶体管用作MOSFET电容器来替代模拟微电路中的无源阱电容器。 双栅极FD-SOI器件的使用有助于减少不稳定的振荡并提高电路性能。 在FD-SOI晶体管的衬底内的厚的掩埋氧化物层形成电容电介质，其能够维持高于晶体管阈值电压的1.2V-3.3V范围内的高工作电压。 FD-SOI晶体管中的次级栅极用于从背面产生通道，使得即使当第一栅极上的偏置电压较小时，有效电容仍然较高。 掩埋氧化物层的电容进一步用作电源和地之间的去耦电容器。 在一个示例中，双栅极PMOS-FD-SOI晶体管耦合到运算放大器和高电压输出驱动器以产生精密控制的电压基准发生器。 在另一示例中，两个双栅极PMOS和一个双栅极NMOS FD-SOI晶体管耦合到电荷泵，相位频率检测器和电流控制振荡器，以产生高性能锁相环电路，其中去耦电容器 与常规使用的无源阱电容相比，占地面积更小。

    Impedance calibration circuit and method
    320.
    发明授权
    Impedance calibration circuit and method 有权
    阻抗校准电路及方法

    公开(公告)号：US09106219B2

    公开(公告)日：2015-08-11

    申请号：US14075272

    申请日：2013-11-08

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Mayank Kumar Singh ,  Daljeet Kumar ,  Hiten Advani

    IPC: H04L25/02 ,  G11C7/12 ,  H03K19/003

    CPC classification number: H03K19/00346 ,  H04L25/0278 ,  H04L25/0298

    Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

    Abstract translation: 实施例包括具有校准器的阻抗校准电路，该校准器被配置为比较外部节点处的电压电平和阻抗校准电路的内部节点，并且基于该比较来生成输出。 校准器还包括耦合在外部节点和比较器的第一输入端之间以及内部节点和比较器的第二输入端之间的相应滤波器。 滤波器被配置为从内部节点处的可编程电阻器耦合到的芯片地线将对称噪声注入到比较器中。

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