公开(公告)号：US20130182523A1

公开(公告)日：2013-07-18

申请号：US13791827

申请日：2013-03-08

Applicant: STMicroelectronics S.A. ,  Medtronic, Inc. ,  STMicroelectronics Inc.

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约高SRAM和低SRAM电源电压之间的电压。

公开(公告)号：US20130181784A1

公开(公告)日：2013-07-18

申请号：US13745613

申请日：2013-01-18

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Yvan Morandini ,  Romain Debrouke

IPC: H01L29/93 ,  H03B1/00 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/66174 ,  H03B1/00 ,  H03B5/1212 ,  H03B5/1253 ,  H03J3/20 ,  H03J2200/10

Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.

Abstract translation: 一种可变电容装置，包括：第一和第二晶体管并联耦合在电容性装置的第一和第二节点之间，第一晶体管的控制节点适于接收控制信号，第二晶体管的控制节点适于接收 控制信号的反相，其中第一和第二晶体管形成在相同的半导体阱中。

公开(公告)号：US20130140693A1

公开(公告)日：2013-06-06

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10um，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连层的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US20130113017A1

公开(公告)日：2013-05-09

申请号：US13628614

申请日：2012-09-27

Applicant: STMicroelectronics S.A.

Inventor： Philippe Galy ,  Jean Jimenez ,  Johan Bourgeat ,  Boris Heitz

IPC: H01L29/747

CPC classification number: H01L27/0262 ,  H01L29/747

Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract translation: 保护装置包括三端双向可控硅开关元件和触发单元。 每个触发单元由配置成至少在混合操作模式中暂时操作的MOS晶体管和场效应二极管形成。 场效应二极管具有连接到MOS晶体管的栅极的受控栅极。

公开(公告)号：US20040263220A1

公开(公告)日：2004-12-30

申请号：US10877747

申请日：2004-06-25

Applicant: STMicroelectronics S.A.

Inventor： Marc Sabut ,  Francois Van Zanten ,  Jean-Luc Moro

IPC: H03B001/00

CPC classification number: H03K17/102 ,  H03K3/356147 ,  H03K17/063

Abstract: A device for controlling a voltage-controlled switch from a digital signal, comprising: a first means for providing the digital signal to the output terminal of the switch; a second means for biasing the switch control terminal to a level greater than the threshold voltage of the switch and smaller than the sum of said threshold voltage and of the maximum voltage of the digital signal; and a third means for adding or subtracting to said level said maximum voltage of the digital signal respectively at the rising and falling edges of the logic inverse of the digital signal.

Abstract translation: 一种用于从数字信号控制压控开关的装置，包括：第一装置，用于将数字信号提供给开关的输出端; 用于将开关控制端子偏置到大于开关的阈值电压的电平并小于所述阈值电压和数字信号的最大电压之和的第二装置; 以及第三装置，用于在数字信号的逻辑反相的上升沿和下降沿分别将数字信号的最大电压加到或减去所述电平。

公开(公告)号：US20040259512A1

公开(公告)日：2004-12-23

申请号：US10819367

申请日：2004-04-06

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Pierre-Oliver Jouffre ,  Bruno Paille

IPC: H04B001/18 ,  H04B001/28

CPC classification number: H04N5/4446 ,  H03D7/165 ,  H04B1/28 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/426 ,  H04N21/6112

Abstract: An integrated superheterodyne dual-conversion tuner upconverts a signal so as to place it outside a reception band, and then downconverts the signal with a non-zero intermediate frequency. A first filter of the bulk acoustic wave type is positioned between the up and down conversion and is calibrated in such a way as to accurately determine its central frequency. A second filter of a microelectromechanical type receives the downconverted signal and is calibrated in such a way as to accurately determine its central frequency.

Abstract translation: 集成的超外差双转换调谐器将信号上变频以将其置于接收频带外，然后以非零中频下变频信号。 体声波型的第一滤波器位于上下转换之间，并且以这样的方式进行校准，以便准确地确定其中心频率。 微机电类型的第二滤波器接收下变频信号，并且以这样一种精确地确定其中心频率的方式进行校准。

公开(公告)号：US20040257480A1

公开(公告)日：2004-12-23

申请号：US10814621

申请日：2004-03-31

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Daniel Saias ,  Frederic Paillardet ,  Franck Montaudon

IPC: H04N005/50

CPC classification number: H04N5/4446 ,  H03D3/007 ,  H03D7/161 ,  H04L2027/0016 ,  H04L2027/0024 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/426 ,  H04N21/6112

Abstract: A dual-conversion tuner firstly upconverts so as to place itself outside the receive band and then downconverts with zero intermediate frequency. A filter of the surface acoustic wave type is disposed between the two frequency transposition stages of the tuner. After baseband filtering, the signals are digitized then processed in a digital block comprising a channel decoding module. With the exception of the surface acoustic wave filter, the components are entirely embodied in integrated fashion.

Abstract translation: 首先将双转换调谐器上变频，将其自身置于接收频带外，然后以零中频下变频。 表面声波型滤波器设置在调谐器的两个频率转置级之间。 在基带滤波之后，信号被数字化，然后在包括信道解码模块的数字块中进行处理。 除了表面声波滤波器之外，组件完全以整体方式体现。

公开(公告)号：US20040252568A1

公开(公告)日：2004-12-16

申请号：US10816204

申请日：2004-04-01

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C011/34

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C2207/063

Abstract: The present invention relates to a sense amplifier for reading a memory cell, comprising a read node linked directly or indirectly to the memory cell, a first active branch connected to the read node, comprising means for supplying a read current at the read node, and a data output linked to one node of the first active branch at which a voltage representative of the conductivity state of the memory cell appears. According to the present invention, the sense amplifier comprises a second active branch connected to the read node, comprising means for supplying, at the read node, a current that is added to the current supplied by the first active branch, such that the voltage representative of the conductivity state of the memory cell remains substantially stable upon a current draw at the read node. Application particularly to reading non-volatile FLASH and EEPROM type memory cells.

Abstract translation: 本发明涉及用于读取存储单元的读出放大器，包括直接或间接地连接到存储单元的读节点，连接到读节点的第一活动分支，包括用于在读节点提供读电流的装置，以及 连接到第一有效分支的一个节点的数据输出，在该节点处表示存储单元的电导率状态的电压。 根据本发明，感测放大器包括连接到读节点的第二有源分支，包括用于在读节点处提供与第一有源分支提供的电流相加的电流的装置，使得电压代表 在读取节点上的电流消耗时，存储单元的导电性状态保持基本稳定。 特别适用于读取非易失性FLASH和EEPROM型存储单元。

公开(公告)号：US20040252245A1

公开(公告)日：2004-12-16

申请号：US10819086

申请日：2004-04-06

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Pierre-Oliver Jouffre ,  Bruno Paille

IPC: H04N005/455

CPC classification number: H03D7/161 ,  H04N5/4401 ,  H04N21/426 ,  H04N21/6112

Abstract: An integrated circuit includes a dual-conversion tuner, firstly upconverting so as to place a signal outside the reception band, then downconverting with zero intermediate frequency. A bulk acoustic wave type filter is calibrated in such a way as to accurately determine its central frequency. This filter is positioned between the two frequency transposition stages of the tuner. After baseband filtering, the signals are digitized then processed in a digital block BNM which includes a channel decoding module.

Abstract translation: 集成电路包括双转换调谐器，首先上变频以将信号放在接收频带外，然后以零中频下变频。 体积声波型滤波器被校准，以便准确地确定其中心频率。 该滤波器位于调谐器的两个频率转置级之间。 在基带滤波之后，信号被数字化，然后在包括信道解码模块的数字块BNM中进行处理。

公开(公告)号：US20040221187A1

公开(公告)日：2004-11-04

申请号：US10774313

申请日：2004-02-06

Applicant: STMicroelectronics S.A.

Inventor： Benoit Durand ,  Jerome Lacan

IPC: G06F001/26

CPC classification number: G06F1/3203 ,  Y02D10/126

Abstract: The present invention relates to an integrated circuit comprising a central processing unit clocked by a clock signal, a main oscillator circuit supplying a first clock signal and a peripheral circuit supplying a periodic wake up signal, the central processing unit comprising a first operating mode at full power, in which the first clock signal is applied to the central processing unit, and an active halt mode in which the main oscillator circuit and the central processing unit are deactivated, the central processing unit being awakened by the periodic wake-up signal. According to the present invention, the integrated circuit comprises a secondary oscillator circuit for supplying a second clock signal of lower frequency than the first clock signal and a circuit for managing clock signals arranged for, upon the wake-up of the central processing unit at the end of the active halt mode, waking up the secondary oscillator circuit and applying the second clock signal to the central processing unit so as to clock the central processing unit to the lower frequency of the second clock signal and thus obtain a second operating mode with reduced current consumption relative to the first operating mode.