公开(公告)号：US20240111457A1

公开(公告)日：2024-04-04

申请号：US18496887

申请日：2023-10-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F3/06 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/00

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US20240111449A1

公开(公告)日：2024-04-04

申请号：US18367789

申请日：2023-09-13

Applicant: RAMBUS INC.

Inventor： Christopher Haywood ,  Frederick A. Ware

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673

Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

公开(公告)号：US11947474B2

公开(公告)日：2024-04-02

申请号：US17830838

申请日：2022-06-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11942182B2

公开(公告)日：2024-03-26

申请号：US18089668

申请日：2022-12-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US11914508B2

公开(公告)日：2024-02-27

申请号：US17065082

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US11899597B2

公开(公告)日：2024-02-13

申请号：US17649773

申请日：2022-02-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/00 ,  G06F13/4243

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US11899571B2

公开(公告)日：2024-02-13

申请号：US17673277

申请日：2022-02-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G06F12/0292

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US20230409499A1

公开(公告)日：2023-12-21

申请号：US18138667

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US20230388028A1

公开(公告)日：2023-11-30

申请号：US18138087

申请日：2023-04-23

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/11 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04B17/21 ,  H04B17/00

CPC classification number: H04B17/11 ,  H04L7/0004 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00 ,  H04B17/21 ,  H04L7/0016 ,  H04L7/0087 ,  H04B17/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US20230377632A1

公开(公告)日：2023-11-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G11C11/4096 ,  G06F11/1048 ,  G11C7/02 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.