公开(公告)号：US11892958B2

公开(公告)日：2024-02-06

申请号：US17667515

申请日：2022-02-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G06F13/16 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2213/0016

Abstract: The present description concerns attribution, on a communication over an I2C bus, of a first address to a first device by a second device, wherein the second device sends the first address over the I2C bus and, if the second device receives no acknowledgment data, then the first device records the first address.

公开(公告)号：US20240030357A1

公开(公告)日：2024-01-25

申请号：US18224293

申请日：2023-07-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/8725 ,  H01L29/66143 ,  H01L29/0619

Abstract: A semiconductor device includes a Schottky diode on a substrate. The Schottky diode includes a layer of polysilicon disposed on a dielectric layer within the substrate that is configured to electrically insulate the layer of polysilicon from the substrate. The layer of polysilicon includes an N-type doped first cathode region adjacent to an undoped second anode region. A first metal contact is disposed on a surface of the N-type doped first cathode region and a second metal contact is disposed on a surface of the undoped second anode region. The first metal contact and second metal contact are electrically insulated from each other by an insulating layer on the layer of polysilicon.

公开(公告)号：US20240014819A1

公开(公告)日：2024-01-11

申请号：US17861067

申请日：2022-07-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Jean-Francois LINK ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/17736 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1737 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20240006896A1

公开(公告)日：2024-01-04

申请号：US18346494

申请日：2023-07-03

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Patrick Arnould ,  Alexandre Tramoni

IPC: H02J7/00

CPC classification number: H02J7/0031 ,  H02J7/0063

Abstract: In accordance with an embodiment, a circuit for managing a power supply of an electronic module includes: a first state machine configured to receive a first command for disabling the module, and to verify that the first command remains the same for a first minimum time period; and a second state machine configured to cut off a power supply of a first portion of the module when the second state machine receives a second command from the first state machine indicating that the first command has remained the same for the first minimum time period. The first portion of the module is configured to is configured to be powered from a battery via a first power supply voltage.

公开(公告)号：US20230403553A1

公开(公告)日：2023-12-14

申请号：US18205839

申请日：2023-06-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent TABARIES

IPC: H04W12/06 ,  H04W12/106

CPC classification number: H04W12/06 ,  H04W12/106

Abstract: Disclosed herein is an electronic control unit including a communication circuit designed to receive intelligent transport system (ITS) messages, an authentication circuit for authenticating the received messages, and a secure element containing a hardware-secure non-volatile memory and a continually active clock counter. The secure element is configured to assign a timestamp data item from the clock counter to each of the authenticated received messages and to store the authenticated messages along with their respective timestamp data in the hardware-secure non-volatile memory

公开(公告)号：US20230387293A1

公开(公告)日：2023-11-30

申请号：US18228309

申请日：2023-07-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Rosalia Germana-Carpineto

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66734

Abstract: A transistor is disclosed. In an embodiment a transistor includes a first semiconductor region of a substrate, a first trench delimiting the first semiconductor region on a first side, a first electrically-conductive element located in the first trench, a channel area in contact with the first semiconductor region and a first area of contact with the first semiconductor region, wherein the channel area and the first area of contact are on the same surface side of the substrate.

公开(公告)号：US11830777B2

公开(公告)日：2023-11-28

申请号：US17863137

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric Gay ,  Abderrezak Marzaki

IPC: H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/74 ,  H01L21/04 ,  H01L21/48 ,  H01L21/76

CPC classification number: H01L21/8249 ,  H01L21/04 ,  H01L21/4803 ,  H01L21/74 ,  H01L21/76 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/732

Abstract: A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

公开(公告)号：US20230378311A1

公开(公告)日：2023-11-23

申请号：US18197420

申请日：2023-05-15

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Guillaume GUIRLEO ,  Abderrezak MARZAKI ,  Thomas CABOUT

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L29/66136 ,  H01L21/02381 ,  H01L21/308 ,  H01L21/0262 ,  H01L21/02293 ,  H01L21/76224

Abstract: A method of manufacturing a PN junction includes successive steps for: forming at least one trench in a semiconductor substrate of a first conductivity type; and filling the at least one trench with a semiconductor material of a second conductivity type, different from the first conductivity type.

公开(公告)号：US11818901B2

公开(公告)日：2023-11-14

申请号：US17489425

申请日：2021-09-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Jean Jacques Fagot ,  Emmanuel Petitprez ,  Emeline Souchier ,  Olivier Weber

IPC: H01L21/8222 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/32 ,  H10N70/231 ,  H10N70/826

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US11817149B2

公开(公告)日：2023-11-14

申请号：US17930250

申请日：2022-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C14/00

CPC classification number: G11C14/0063

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.