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    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
    332.
    发明申请
    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US20160086962A1

    公开(公告)日：2016-03-24

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L27/115 ,  H01L21/762 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Double patterning method of forming semiconductor active areas and isolation regions
    333.
    发明授权
    Double patterning method of forming semiconductor active areas and isolation regions 有权
    形成半导体有源区和隔离区的双重图案化方法

    公开(公告)号：US09293358B2

    公开(公告)日：2016-03-22

    申请号：US14162309

    申请日：2014-01-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Chien-Sheng Su

    IPC: H01L21/336 ,  H01L21/762 ,  H01L21/308

    CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

    Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

    Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。

    Non-volatile memory cell with self aligned floating and erase gates, and method of making same
    334.
    发明授权
    Non-volatile memory cell with self aligned floating and erase gates, and method of making same 有权
    具有自对准浮动和擦除栅极的非易失性存储单元及其制造方法

    公开(公告)号：US09293204B2

    公开(公告)日：2016-03-22

    申请号：US14252929

    申请日：2014-04-15

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

    IPC: H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

    Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

    Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

    Non-volatile Memory Device And A Method Of Programming Such Device
    340.
    发明申请
    Non-volatile Memory Device And A Method Of Programming Such Device 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US20150003166A1

    公开(公告)日：2015-01-01

    申请号：US14449926

    申请日：2014-08-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

    IPC: G11C16/10 ,  G11C16/26 ,  H01L27/115

    CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

    Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

    Abstract translation: 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

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