公开(公告)号：US09978602B2

公开(公告)日：2018-05-22

申请号：US14923176

申请日：2015-10-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/28 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

公开(公告)号：US20180108731A1

公开(公告)日：2018-04-19

申请号：US15845930

申请日：2017-12-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Perrin

IPC: H01L29/06 ,  H01L21/84 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

公开(公告)号：US20180102385A1

公开(公告)日：2018-04-12

申请号：US15592437

申请日：2017-05-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel Benoit ,  Olivier Hinsinger ,  Emmanuel Gourvest

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14698

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

公开(公告)号：US20180102328A1

公开(公告)日：2018-04-12

申请号：US15606212

申请日：2017-05-26

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sébastien Petitdidier ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/573 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/522 ,  H01L23/5226

Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.

公开(公告)号：US09941200B1

公开(公告)日：2018-04-10

申请号：US15275619

申请日：2016-09-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L25/0657

Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.

公开(公告)号：US09941170B2

公开(公告)日：2018-04-10

申请号：US15450114

申请日：2017-03-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Gregory Avenier

IPC: H01L27/102 ,  H01L21/8228 ,  H01L21/761 ,  H01L21/265 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/82285 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/761 ,  H01L27/0623 ,  H01L27/0716 ,  H01L27/1022 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

公开(公告)号：US20180097014A1

公开(公告)日：2018-04-05

申请号：US15722340

申请日：2017-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Vincent Barral ,  Nicolas Planes ,  Antoine Cros ,  Sebastien Haendler ,  Thierry Poiroux ,  Olivier Weber ,  Patrick Scheer

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  B82Y99/00

Abstract: An electronic chip includes FDSOI-type field-effect transistors. The transistor each have a channel region that is doped at an average level in a range from 1016 to 5*1017 atoms/cm3 with a conductivity type opposite to that of a conductivity type for the dopant in the drain and source regions.

公开(公告)号：US20180090389A1

公开(公告)日：2018-03-29

申请号：US15458109

申请日：2017-03-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Guillaume C. Ribes ,  Benjamin Dumont ,  Franck Arnaud

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7838

Abstract: An integrated circuit includes FDSOI-type MOS transistors formed inside and on top of a semiconductor layer resting on an insulating layer. The transistors include a logic MOS transistor of a first conductivity type, a logic MOS transistor of a second conductivity type, and an analog MOS transistor of the first conductivity type, A gate stack of the logic transistors successively includes a gate insulator layer, a first titanium nitride layer, a lanthanum layer, and a second titanium nitride layer. A gate stack of the analog transistor includes the gate insulator layer, the lanthanum layer and the second titanium nitride layer but not the first titanium nitride layer.

公开(公告)号：US09929720B2

公开(公告)日：2018-03-27

申请号：US14847900

申请日：2015-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Quemerais ,  Alice Bossuet ,  Daniel Gloria

IPC: G01R1/067 ,  H03H11/24 ,  H03F3/60

CPC classification number: H03H11/245 ,  G01R1/06711 ,  H03F3/602 ,  H03F2200/211

Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.

公开(公告)号：US20180083057A1

公开(公告)日：2018-03-22

申请号：US15460992

申请日：2017-03-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Axel Crocherie ,  Pierre Emmanuel Marie Malinge

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14649 ,  H01L27/14685

Abstract: An integrated image sensor with backside illumination includes a pixel. The pixel is formed by a photodiode within an active semiconductor region having a first face and a second face. A converging lens, lying in front of the first face of the active region, directs received light rays towards a central zone of the active region. At least one diffracting element, having a refractive index different from a refractive index of the active region, is provided at least partly aligned with the central zone at one of the first and second faces.