公开(公告)号：US20130322039A1

公开(公告)日：2013-12-05

申请号：US13485631

申请日：2012-05-31

Applicant: Jerome Teysseyre ,  Glenn de los Reyes ,  Wee Chin Judy Lim

Inventor： Jerome Teysseyre ,  Glenn de los Reyes ,  Wee Chin Judy Lim

IPC: H05K5/02 ,  B05D5/12 ,  B32B37/10 ,  H05K9/00 ,  B32B37/02

CPC classification number: H05K9/003

Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.

Abstract translation: 用于微机电系统装置的盖子包括第一层，例如其中形成有通孔的双马来酰亚胺三嗪（BT）树脂材料，层压到封闭第一层中的孔的第二层BT树脂材料上，形成 一个空腔。 第一层和第二层与热固性粘合剂层压，该热固性粘合剂足够厚以封装可以从用于形成孔的路由操作保留的颗粒。 空腔的内部，包括粘合剂的暴露部分和第一层的暴露表面涂覆有导电涂料。 使用导电粘合剂将盖子粘附到MEMS装置上的基板上，导电粘合剂将导电涂料层耦合到基板的接地平面。 导电涂料层用作屏蔽，以防止或减少作用在MEMS器件上的电磁干扰。

公开(公告)号：US20130314972A1

公开(公告)日：2013-11-28

申请号：US13953626

申请日：2013-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：US20130168815A1

公开(公告)日：2013-07-04

申请号：US13341286

申请日：2011-12-30

Applicant: Olivier Le Neel ,  Ravi Shankar

Inventor： Olivier Le Neel ,  Ravi Shankar

IPC: H01L27/06 ,  H01L21/02

CPC classification number: G01K7/20 ,  G01K3/005

Abstract: The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off.

Abstract translation: 本公开涉及用于形成具有四个电阻器和比较器的惠斯登电桥配置的精密温度传感器开关的装置和方法。 当温度传感器检测到温度高于阈值时，开关将改变状态。 惠斯通电桥中的四个电阻具有相同的电阻，其中三个电阻具有低的电阻温度系数，第四电阻具有高的电阻温度系数。 随着温度的升高，第四个电阻的电阻将发生变化。 第四个电阻器的电阻变化会改变跨桥的电压。 桥上的电压耦合到比较器并将电压与阈值温度进行比较，使得当超过阈值温度时，比较器关闭输出。

公开(公告)号：US20130168377A1

公开(公告)日：2013-07-04

申请号：US13339757

申请日：2011-12-29

Applicant: Ying Shun Liang ,  Samuel Gordon McKee

Inventor： Ying Shun Liang ,  Samuel Gordon McKee

IPC: F27D11/00 ,  B23P11/00 ,  F03B11/02

CPC classification number: H01L21/67017 ,  Y10T29/49826 ,  Y10T137/8593

Abstract: An adapter is provided for fluidly coupling a process chamber, such as a diffusion furnace or a process tube, and a fluid source, such as a torch chamber or combustion chamber, of a system for processing semiconductor material. The process tube and the torch chamber include joint segments that can engage directly together to fluidly couple the torch chamber to the process tube for introducing a fluid, such as an oxidizing gas or vapor, into the process tube. The process chamber and the torch chamber are formed of materials having different rates of thermal expansion. The adapter is configured to couple the joint segments of the torch chamber and the process tube while accommodating the differences in thermal expansion between the materials. The adapter may be formed of quartz to couple a quartz torch chamber with a silicon carbide process tube.

Abstract translation: 提供了用于流体耦合诸如扩散炉或处理管的处理室和用于处理半导体材料的系统的流体源（例如割炬室或燃烧室）的适配器。 处理管和割炬室包括可以直接接合在一起以将炬室流体连接到处理管的接合段，用于将诸如氧化气体或蒸气的流体引入到处理管中。 处理室和割炬室由具有不同热膨胀率的材料形成。 适配器被配置成耦合炬室和处理管的接合部分，同时容纳材料之间的热膨胀差异。 适配器可以由石英形成，以将石英炬室与碳化硅工艺管连接。

公开(公告)号：US20130164867A1

公开(公告)日：2013-06-27

申请号：US13335548

申请日：2011-12-22

Applicant: Anandan Ramasamy ,  KahWee Gan ,  Hk Looi ,  David Gani

Inventor： Anandan Ramasamy ,  KahWee Gan ,  Hk Looi ,  David Gani

IPC: H01L33/48

CPC classification number: H01L25/167 ,  H01L23/5389 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14683 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.

Abstract translation: 一种形成嵌入式晶片级光学封装的方法包括将传感器芯片，PCB条和LED粘贴在层压在载体上的粘合带上，将传感器管芯的两个感光传感器之间的坝连接，封装传感器管芯，PCB条 ，LED和封装层中的坝，使载体脱粘，研磨封装层的顶表面，通过封装层形成通孔到传感器裸片和LED，用导电材料填充通孔，使顶表面金属化 封装层的顶表面的电介质涂层，封装层的底表面的电介质涂层，图案化封装层底表面的电介质涂层，以及镀覆底表面的图案化电介质涂层 的封装层。

公开(公告)号：US20130141834A1

公开(公告)日：2013-06-06

申请号：US13310466

申请日：2011-12-02

Applicant: Olivier Le Neel ,  Ravi Shankar

Inventor： Olivier Le Neel ,  Ravi Shankar

IPC: H01G4/00 ,  H01G7/04 ,  H05K7/06

CPC classification number: H01G7/04 ,  H01G4/33 ,  H01L23/345 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0688 ,  H01L28/40 ,  H01L28/55 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

Abstract: The present disclosure is directed to a device and a method for achieving a precise capacitance of a capacitor. The method includes trimming a first capacitance of the capacitor to a second capacitance, the capacitor having a first conductive layer separated from a second conductive layer by a dielectric layer. Changing a first dielectric constant of the dielectric layer to a second dielectric constant, where the first dielectric constant corresponding to the first capacitance and the second dielectric constant corresponding to the second dielectric constant includes heating the dielectric layer above a threshold temperature for a time period. The heat is provided by either one of the plates of the capacitor or from a separate heater.

Abstract translation: 本公开涉及一种用于实现电容器的精确电容的装置和方法。 该方法包括将电容器的第一电容调整为第二电容，该电容器具有通过电介质层与第二导电层分离的第一导电层。 将电介质层的第一介电常数改变到第二介电常数，其中对应于第一电容的第一介电常数和对应于第二介电常数的第二介电常数包括将电介质层加热到阈值温度一段时间。 热量由电容器的任一个板或从单独的加热器提供。

公开(公告)号：US20130113098A1

公开(公告)日：2013-05-09

申请号：US13291788

申请日：2011-11-08

Applicant: How Yuan Hwang ,  Kah Wee Gan

Inventor： How Yuan Hwang ,  Kah Wee Gan

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/023 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.

公开(公告)号：US08436426B2

公开(公告)日：2013-05-07

申请号：US12862594

申请日：2010-08-24

Applicant: Olivier Le Neel ,  Calvin Leung

Inventor： Olivier Le Neel ,  Calvin Leung

IPC: H01L23/62

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L28/24 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.

Abstract translation: 本公开涉及具有第一电阻温度系数的第一电阻层和第一电阻层上的第二电阻层的薄膜电阻器，第二电阻层具有与第一温度系数不同的第二温度系数 的阻力。 电阻的第一温度系数可以为正，而第二温度系数为负。 第一电阻层可以具有在50和150埃范围内的厚度，并且第二电阻层的厚度可以在20和50埃的范围内。

公开(公告)号：US08436255B2

公开(公告)日：2013-05-07

申请号：US12651295

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H05K1/11

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/293 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2224/03334 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05571 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/221 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80815 ,  H01L2224/814 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3025 ,  Y10T29/49117 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.

Abstract translation: 包含电子封装中的球栅阵列的焊料元件的聚合物层。 聚合物层通过将球栅阵列的元件包围在粘合到封装结构的刚性聚合物层中来加强焊球组分界面处的焊料接合。 通过球栅阵列施加到封装的应力通过聚合物层传递到封装结构，绕过焊点并改善机电电路的可靠性。 在制造聚合物层的方法的一个实施方案中，与封装结构上的外部焊盘接合的焊料元素浸没在聚合物层的流体形式中。 流体形式被固化，然后去除所得聚合物层的一部分，以使焊料元件可接近以将封装安装到印刷电路板或其它外部电路。

公开(公告)号：US20130093072A1

公开(公告)日：2013-04-18

申请号：US13273027

申请日：2011-10-13

Applicant: Xueren Zhang ,  Wingshenq Wong ,  Kim-Yong Goh ,  Yiyi Ma

Inventor： Xueren Zhang ,  Wingshenq Wong ,  Kim-Yong Goh ,  Yiyi Ma

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/49513 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00

Abstract: A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die.

Abstract translation: 引线框架包括芯片焊盘和围绕芯片焊盘的保护壁。 半导体管芯位于管芯焊盘上。 在与半导体管芯的角部相邻的保护壁的四个内角上形成有凹痕。