公开(公告)号：US08617987B2

公开(公告)日：2013-12-31

申请号：US12982697

申请日：2010-12-30

申请人： Kah Wee Gan ,  Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

发明人： Kah Wee Gan ,  Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L25/105 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  Y10T29/413 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00

摘要： An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

摘要翻译： 嵌入式晶片级球栅阵列（eWLB）通过将半导体管芯嵌入到模塑料中而形成。 在激光钻头的模塑料中形成沟槽。 第一层铜通过物理气相沉积沉积在沟槽的侧壁上。 然后通过无电解方法在第一层铜上形成第二层铜层。 然后通过电镀在第二层上形成第三层铜层。

公开(公告)号：US20130113098A1

公开(公告)日：2013-05-09

申请号：US13291788

申请日：2011-11-08

申请人： How Yuan Hwang ,  Kah Wee Gan

发明人： How Yuan Hwang ,  Kah Wee Gan

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L21/50

CPC分类号： H01L24/14 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/023 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.

公开(公告)号：US20120171875A1

公开(公告)日：2012-07-05

申请号：US12982707

申请日：2010-12-30

申请人： Kah Wee Gan ,  Yonggang Jin

发明人： Kah Wee Gan ,  Yonggang Jin

IPC分类号： H01L21/324 ,  F27D3/00

CPC分类号： H01L21/67288

摘要： A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

摘要翻译： 一种减少半导体晶片翘曲的系统和方法。 该系统包括用于将半导体晶片固定在加热区域中的装置。 该装置包括用于固定半导体晶片的边缘的保持机构。 该装置还包括减压装置，其降低半导体器件下方的压力，这进一步将半导体器件固定在加热区域中。 加热区域包括多个加热和冷却区域，其中半导体晶片经受各种温度。

公开(公告)号：US20120168943A1

公开(公告)日：2012-07-05

申请号：US12982719

申请日：2010-12-30

申请人： Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

发明人： Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

IPC分类号： H01L23/485 ,  H01L21/50

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014

摘要： A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package.

摘要翻译： 描述了半导体封装及其形成方法。 半导体封装由从具有钝化层的半导体晶片切割的半导体管芯形成。 将半导体晶片暴露于电离气体，导致钝化层变粗糙。 切割半导体晶片以形成多个具有粗糙化钝化层的半导体管芯。 多个半导体管芯被放置在粘合剂层上以形成重构的晶片，并且形成包封粘合剂层和多个半导体管芯的封装层。 去除钝化层，形成的半导体封装包括用于在半导体封装外部建立电连接的电触头。

公开(公告)号：US08922013B2

公开(公告)日：2014-12-30

申请号：US13291788

申请日：2011-11-08

申请人： How Yuan Hwang ,  Kah Wee Gan

发明人： How Yuan Hwang ,  Kah Wee Gan

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L24/14 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/023 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.

摘要翻译： 集成电路封装包括在复原衬底中的集成电路管芯。 然后将活性侧加工成模塑料，同时处理非活性侧。 然后部分地去除活性侧上的模塑料，并且在活性侧上放置焊球。

公开(公告)号：US08916481B2

公开(公告)日：2014-12-23

申请号：US13312562

申请日：2011-12-06

申请人： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

发明人： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

IPC分类号： H01L21/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L25/10 ,  H05K1/18

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K1/186 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.

摘要翻译： 一种用于制造3D或PoP半导体封装的工艺包括在再构成的晶片上形成再分配层，然后激光钻出重建的晶片中的多个孔，从再构成的晶片的外表面延伸，以与第一再分配层 。 然后将焊球定位成与每个孔的开口相邻。 焊球熔化并允许填充孔，与相应的电迹线接触并形成多个焊料柱。 然后将重构的晶片的外表面平坦化，并且在平坦化表面上形成第二再分布层。 焊料柱用作通孔，将重新构成的晶片的相对侧上的第一和第二再分配层电耦合。

公开(公告)号：US08728831B2

公开(公告)日：2014-05-20

申请号：US12982707

申请日：2010-12-30

申请人： Kah Wee Gan ,  Yonggang Jin

发明人： Kah Wee Gan ,  Yonggang Jin

IPC分类号： H01L21/00

CPC分类号： H01L21/67288

摘要： A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

摘要翻译： 一种减少半导体晶片翘曲的系统和方法。 该系统包括用于将半导体晶片固定在加热区域中的装置。 该装置包括用于固定半导体晶片的边缘的保持机构。 该装置还包括减压装置，其降低半导体器件下方的压力，这进一步将半导体器件固定在加热区域中。 加热区域包括多个加热和冷却区域，其中半导体晶片经受各种温度。

公开(公告)号：US20120282767A1

公开(公告)日：2012-11-08

申请号：US13173991

申请日：2011-06-30

申请人： Yonggang Jin ,  Yun Liu ,  Puay Gek Chua ,  Anandan Ramasamy ,  Yaohuang Huang ,  Kah Wee Gan

发明人： Yonggang Jin ,  Yun Liu ,  Puay Gek Chua ,  Anandan Ramasamy ,  Yaohuang Huang ,  Kah Wee Gan

IPC分类号： H01L21/60

CPC分类号： H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed.

摘要翻译： 半导体封装工艺包括在重构的晶片中的钻孔，然后通过在晶片的背面上擦拭一定量的糊料，将导电浆料填充到孔中，使得膏被迫进入孔中。 该膏被固化以形成导电柱。 晶片变薄，并且再分布层形成在晶片的前表面和后表面上，其中柱用作再分布层之间的互连。 在另一种方法中，钻出盲孔。 将干膜抗蚀剂施加到晶片的前表面，并图案化以露出孔。 导电胶从前面涂敷。 为了防止糊料在孔中捕获气穴，擦拭过程在真空下进行。 固化糊剂后，将晶片变薄以露出孔中的固化糊料，形成再分布层。

公开(公告)号：US08779601B2

公开(公告)日：2014-07-15

申请号：US13287826

申请日：2011-11-02

申请人： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

发明人： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/48 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.

摘要翻译： 用于3D和PoP应用的eWLB封装包括支撑晶片上的再分配层。 半导体管芯耦合到再分配层，并且焊球也位于再分配层上。 模具和焊球被封装在模制化合物层中，其被平坦化以暴露焊球的顶部部分。 在模塑料层的平坦化表面上形成第二重分布层。 球栅阵列可以位于第二再分配层上以将半导体封装耦合到电路板，或者可以在相应的模制化合物层中添加另外的半导体管芯。 支撑晶片可以用作插入件，在这种情况下，它被处理以形成与第一再分配层电接触的TSV，并且再分配层也形成在支撑衬底的相对侧上。

公开(公告)号：US20130105991A1

公开(公告)日：2013-05-02

申请号：US13312562

申请日：2011-12-06

申请人： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

发明人： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L21/50

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K1/186 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.

摘要翻译： 一种用于制造3D或PoP半导体封装的工艺包括在再构成的晶片上形成再分配层，然后激光钻出重建的晶片中的多个孔，从再构成的晶片的外表面延伸，以与第一再分配层 。 然后将焊球定位成与每个孔的开口相邻。 焊球熔化并允许填充孔，与相应的电迹线接触并形成多个焊料柱。 然后将重构的晶片的外表面平坦化，并且在平坦化表面上形成第二再分布层。 焊料柱用作通孔，将重新构成的晶片的相对侧上的第一和第二再分配层电耦合。